VGAPIC32

Annotated mips.h

0:71d6504cb824
2017-05-06 Paul Boddie An attempt to produce VGA output signals with a PIC32 device.
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#ifndef __MIPS_H__
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#define __MIPS_H__
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#define CP0_INDEX	$0
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#define CP0_ENTRYLO0	$2
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#define CP0_ENTRYLO1	$3
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#define CP0_CONTEXT	$4
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#define CP0_PAGEMASK	$5
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#define CP0_WIRED	$6
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#define CP0_ENTRYHI	$10
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#define CP0_STATUS	$12
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#define CP0_INTCTL	$12, 1
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#define CP0_CAUSE	$13
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#define CP0_EPC		$14
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#define CP0_EBASE	$15, 1
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#define CP0_CONFIG	$16
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#define CP0_WATCHLO	$18
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#define CP0_TAGLO	$28
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#define CP0_TAGHI	$29
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#define STATUS_CP0	0x10000000
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#define STATUS_BEV	0x00400000
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#define STATUS_IRQ	0x0000fc00
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#define STATUS_UM	0x00000010
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#define STATUS_ERL	0x00000004
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#define STATUS_EXL	0x00000002
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#define STATUS_IE	0x00000001
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#define CAUSE_IV	0x00800000
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#define EBASE_MASK	0x3ffff000
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#define INTCTL_MASK	0x000003e0
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#define TLB_CACHED	0x00000018
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#define TLB_UNCACHED	0x00000010
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#define TLB_DIRTY	0x00000004
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#define TLB_VALID	0x00000002
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#define TLB_GLOBAL	0x00000001
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#define TLB_READ	(TLB_CACHED | TLB_VALID)
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#define TLB_WRITE	(TLB_CACHED | TLB_DIRTY | TLB_VALID)
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#define TLB_ALL_READ	(TLB_CACHED | TLB_VALID | TLB_GLOBAL)
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#define TLB_ALL_WRITE	(TLB_CACHED | TLB_DIRTY | TLB_VALID | TLB_GLOBAL)
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#define CONFIG_CM_UNCACHED		2
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#define CONFIG_CM_CACHABLE_NONCOHERENT	3
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#endif /* __MIPS_H__ */