77:61443a9bb80f
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2017-11-18 |
Paul Boddie |
changeset
files
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Introduced UART usage to obtain exception details. |
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mips.h pic32.h vga.S
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76:ff962c071724
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2017-11-17 |
Paul Boddie |
changeset
files
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Update timer interrupt priorities atomically, removing disable/enable code. |
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vga.S
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75:7edceda19310
71:0c6e88eb049f
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2017-11-16 |
Paul Boddie |
changeset
files
shortlog
graph
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Reorganised interrupt handling to only test either timer or DMA interrupt
conditions, not both, also merging the execution of the visible/active region
and address update routines within a single call. |
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vga.S
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74:7d1685074d4c
83:0a7176ba81ef
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2017-11-07 |
Paul Boddie |
changeset
files
shortlog
graph
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Reordered channel and timer activation instructions, tidied generally. |
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vga.S
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73:83ebe9cd0314
60:ae02a1821af3
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2017-11-07 |
Paul Boddie |
changeset
files
shortlog
graph
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Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
level), guarding priority changes by disabling and re-enabling the interrupt.
The timer interrupt should probably be enabled during the active display period
for the DMA channels to operate, even though circumstances appear to allow the
channels to function in this configuration with the timer interrupt disabled. |
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mips.h vga.S
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72:a297782bef19
82:f83509c62e12
70:129ef681b3fc
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2017-11-07 |
Paul Boddie |
changeset
files
shortlog
graph
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Reordered channel and timer activation instructions, tidied generally. |
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vga.S
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71:0c6e88eb049f
75:7edceda19310
69:aa1ac5755f03
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2017-11-07 |
Paul Boddie |
changeset
files
shortlog
graph
|
Reordered channel and timer activation instructions, tidied generally. |
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vga.S
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70:129ef681b3fc
72:a297782bef19
66:64546519a57d
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2017-11-07 |
Paul Boddie |
changeset
files
shortlog
graph
|
Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
level), guarding priority changes by disabling and re-enabling the interrupt.
The timer interrupt should probably be enabled during the active display period
for the DMA channels to operate, even though circumstances appear to allow the
channels to function in this configuration with the timer interrupt disabled. |
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mips.h vga.S
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69:aa1ac5755f03
71:0c6e88eb049f
53:9b3b13a62733
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2017-11-07 |
Paul Boddie |
changeset
files
shortlog
graph
|
Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
level), guarding priority changes by disabling and re-enabling the interrupt.
The timer interrupt should probably be enabled during the active display period
for the DMA channels to operate, even though circumstances appear to allow the
channels to function in this configuration with the timer interrupt disabled. |
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mips.h vga.S
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68:ec19e9f803b5
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2017-11-06 |
Paul Boddie |
changeset
files
shortlog
graph
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Enable Timer3 interrupts in order to create timer events. |
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pic32.h vga.S
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