1 #ifndef __PIC32_H__ 2 #define __PIC32_H__ 3 4 /* See... 5 * TABLE 4-1: SFR MEMORYMAP 6 * TABLE 11-3: PORTA REGISTER MAP 7 * 11.2 CLR, SET and INV Registers 8 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 9 */ 10 11 #define OC1CON 0xBF803000 12 #define OC1R 0xBF803010 13 #define OC1RS 0xBF803020 14 #define OC2CON 0xBF803200 15 #define OC2R 0xBF803210 16 #define OC2RS 0xBF803220 17 #define OC3CON 0xBF803400 18 #define OC3R 0xBF803410 19 #define OC3RS 0xBF803420 20 21 #define T1CON 0xBF800600 22 #define TMR1 0xBF800610 23 #define PR1 0xBF800620 24 #define T2CON 0xBF800800 25 #define TMR2 0xBF800810 26 #define PR2 0xBF800820 27 #define T3CON 0xBF800A00 28 #define TMR3 0xBF800A10 29 #define PR3 0xBF800A20 30 31 #define U1MODE 0xBF806000 32 #define U1STA 0xBF806010 33 #define U1TXREG 0xBF806020 34 #define U1RXREG 0xBF806030 35 #define U1BRG 0xBF806040 36 37 #define PMCON 0xBF807000 38 #define PMMODE 0xBF807010 39 #define PMADDR 0xBF807020 40 #define PMDOUT 0xBF807030 41 #define PMDIN 0xBF807040 42 #define PMAEN 0xBF807050 43 #define PMSTAT 0xBF807060 44 45 #define OSCCON 0xBF80F000 46 #define REFOCON 0xBF80F020 47 #define REFOTRIM 0xBF80F030 48 #define CFGCON 0xBF80F200 49 #define SYSKEY 0xBF80F230 50 51 #define U1RXR 0xBF80FA50 52 53 #define RPA0R 0xBF80FB00 54 #define RPA1R 0xBF80FB04 55 #define RPA2R 0xBF80FB08 56 #define RPA3R 0xBF80FB0C 57 #define RPA4R 0xBF80FB10 58 #define RPB0R 0xBF80FB2C 59 #define RPB1R 0xBF80FB30 60 #define RPB2R 0xBF80FB34 61 #define RPB3R 0xBF80FB38 62 #define RPB4R 0xBF80FB3C 63 #define RPB5R 0xBF80FB40 64 #define RPB10R 0xBF80FB54 65 #define RPB15R 0xBF80FB68 66 67 #define INTCON 0xBF881000 68 #define IFS0 0xBF881030 69 #define IFS1 0xBF881040 70 #define IEC0 0xBF881060 71 #define IEC1 0xBF881070 72 #define IPC1 0xBF8810A0 73 #define IPC2 0xBF8810B0 74 #define IPC3 0xBF8810C0 75 #define IPC7 0xBF881100 76 #define IPC8 0xBF881110 77 #define IPC10 0xBF881130 78 79 #define BMXCON 0xBF882000 80 #define BMXDKPBA 0xBF882010 81 #define BMXDUDBA 0xBF882020 82 #define BMXDUPBA 0xBF882030 83 #define BMXDRMSZ 0xBF882040 84 85 #define DMACON 0xBF883000 86 #define DCH0CON 0xBF883060 87 #define DCH0ECON 0xBF883070 88 #define DCH0INT 0xBF883080 89 #define DCH0SSA 0xBF883090 90 #define DCH0DSA 0xBF8830A0 91 #define DCH0SSIZ 0xBF8830B0 92 #define DCH0DSIZ 0xBF8830C0 93 #define DCH0CSIZ 0xBF8830F0 94 #define DCH1CON 0xBF883120 95 #define DCH1ECON 0xBF883130 96 #define DCH1INT 0xBF883140 97 #define DCH1SSA 0xBF883150 98 #define DCH1DSA 0xBF883160 99 #define DCH1SSIZ 0xBF883170 100 #define DCH1DSIZ 0xBF883180 101 #define DCH1CSIZ 0xBF8831B0 102 #define DCH2CON 0xBF8831E0 103 #define DCH2ECON 0xBF8831F0 104 #define DCH2INT 0xBF883200 105 #define DCH2SSA 0xBF883210 106 #define DCH2DSA 0xBF883220 107 #define DCH2SSIZ 0xBF883230 108 #define DCH2DSIZ 0xBF883240 109 #define DCH2CSIZ 0xBF883270 110 111 #define ANSELA 0xBF886000 112 #define TRISA 0xBF886010 113 #define PORTA 0xBF886020 114 #define LATA 0xBF886030 115 #define ODCA 0xBF886040 116 #define ANSELB 0xBF886100 117 #define TRISB 0xBF886110 118 #define PORTB 0xBF886120 119 #define LATB 0xBF886130 120 #define ODCB 0xBF886140 121 122 #define CLR 0x4 123 #define SET 0x8 124 #define INV 0xC 125 126 #endif /* __PIC32_H__ */