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Fill the display by using a 30MHz clock and adjusted timings. |
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Switched to using PORTB instead of PMDIN for pixel data output. |
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Update the cache status in the config register. |
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Added initial documentation. |
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Fixed bitfield information in comment. |
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Tidied up the comments somewhat. |
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Simplified the horizontal line details; introduced bus arbitration mode 2 usage. |
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Introduced interrupt and exception initialisation fixes plus a revised state |
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Update the DMA source address without disabling the channel. |
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Added support for updating the line data address after every other transfer. |
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Added line address variable (to be used) and adjusted IRQ label names. |
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Introduced output compare usage with Timer2 to generate the hsync pulse for each |
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Switch to Timer2 usage from Timer1. |
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Tidied and incorporated some aspects of working PMP and DMA tests. |
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Added some definitions for memory areas and DMA. |
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Introduced the framework implementing different vertical signal periods. |
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An attempt to produce VGA output signals with a PIC32 device. |
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