# HG changeset patch # User Paul Boddie # Date 1649003966 -7200 # Node ID 8c68efc3a951e4c31b6ba4a0e343572e0d56e092 # Parent 75a233ccc2c5ba2eab129ad9d1fb88ac1dea5676 Added alternative TM4164EA4 RAM module. Changed RAM outputs to tri-state. diff -r 75a233ccc2c5 -r 8c68efc3a951 AcornElectron.lib --- a/AcornElectron.lib Sun Feb 27 17:46:10 2022 +0100 +++ b/AcornElectron.lib Sun Apr 03 18:39:26 2022 +0200 @@ -1,6 +1,34 @@ EESchema-LIBRARY Version 2.4 #encoding utf-8 # +# 4164 +# +DEF 4164 U 0 40 Y Y 1 F N +F0 "U" 0 550 50 H V C CNN +F1 "4164" 0 450 50 H V C CNN +F2 "" -50 0 50 H I C CNN +F3 "" -50 0 50 H I C CNN +DRAW +S -250 400 250 -400 0 1 0 f +X NC 1 -350 350 100 R 50 50 1 1 N +X A5 10 350 -250 100 L 50 50 1 1 I +X A4 11 350 -150 100 L 50 50 1 1 I +X A3 12 350 -50 100 L 50 50 1 1 I +X A6 13 350 50 100 L 50 50 1 1 I +X DO 14 350 150 100 L 50 50 1 1 T +X ~CAS 15 350 250 100 L 50 50 1 1 I +X VSS 16 350 350 100 L 50 50 1 1 W +X DI 2 -350 250 100 R 50 50 1 1 I +X ~WE 3 -350 150 100 R 50 50 1 1 I +X ~RAS 4 -350 50 100 R 50 50 1 1 I +X A0 5 -350 -50 100 R 50 50 1 1 I +X A2 6 -350 -150 100 R 50 50 1 1 I +X A1 7 -350 -250 100 R 50 50 1 1 I +X VCC 8 -350 -350 100 R 50 50 1 1 W +X A7 9 350 -350 100 L 50 50 1 1 I +ENDDRAW +ENDDEF +# # 6502A # DEF 6502A U 0 40 Y Y 1 F N @@ -110,6 +138,40 @@ ENDDRAW ENDDEF # +# TM4164EA4 +# +DEF TM4164EA4 U 0 40 Y Y 1 F N +F0 "U" 0 1600 50 H V C CNN +F1 "TM4164EA4" 0 1700 50 H V C CNN +F2 "" 50 500 50 H I C CNN +F3 "" 50 500 50 H I C CNN +DRAW +S -250 1150 250 -1150 0 1 0 f +X NC 1 350 -650 100 L 50 50 1 1 N +X Q2 10 350 750 100 L 50 50 1 1 T +X ~W 11 350 -1050 100 L 50 50 1 1 I +X A1 12 350 50 100 L 50 50 1 1 I +X A3 13 350 -150 100 L 50 50 1 1 I +X A6 14 350 -450 100 L 50 50 1 1 I +X Q3 15 350 550 100 L 50 50 1 1 T +X D3 16 350 650 100 L 50 50 1 1 I +X A2 17 350 -50 100 L 50 50 1 1 I +X A0 18 350 150 100 L 50 50 1 1 I +X ~RAS 19 350 -950 100 L 50 50 1 1 I +X VDD 2 0 1250 100 D 50 50 1 1 W +X D4 20 350 450 100 L 50 50 1 1 I +X Q4 21 350 350 100 L 50 50 1 1 T +X VSS 22 0 -1250 100 U 50 50 1 1 W +X D1 3 350 1050 100 L 50 50 1 1 I +X Q1 4 350 950 100 L 50 50 1 1 T +X ~CAS 5 350 -850 100 L 50 50 1 1 I +X A7 6 350 -550 100 L 50 50 1 1 I +X A5 7 350 -350 100 L 50 50 1 1 I +X A4 8 350 -250 100 L 50 50 1 1 I +X D2 9 350 850 100 L 50 50 1 1 I +ENDDRAW +ENDDEF +# # ULA12C021 # DEF ULA12C021 U 0 40 Y Y 1 F N diff -r 75a233ccc2c5 -r 8c68efc3a951 AcornElectronMainboard.sch --- a/AcornElectronMainboard.sch Sun Feb 27 17:46:10 2022 +0100 +++ b/AcornElectronMainboard.sch Sun Apr 03 18:39:26 2022 +0200 @@ -463,8 +463,6 @@ $EndSheet Wire Bus Line 2100 2300 1700 2300 -Wire Bus Line - 2100 1600 1700 1600 Text GLabel 1700 1600 0 50 BiDi ~ 0 RAM[0..3] Text GLabel 1700 2300 0 50 Output ~ 0 @@ -985,6 +983,8 @@ Text Notes 4550 1400 0 50 ~ 0 Note that KiCad gets upset\nwhen connecting passives\nto power input pins. Wire Bus Line + 1700 1600 2100 1600 +Wire Bus Line 2100 1600 2100 1900 Wire Bus Line 2100 3100 2100 3400 diff -r 75a233ccc2c5 -r 8c68efc3a951 RAM.sch --- a/RAM.sch Sun Feb 27 17:46:10 2022 +0100 +++ b/RAM.sch Sun Apr 03 18:39:26 2022 +0200 @@ -15,7 +15,7 @@ Comment4 "" $EndDescr $Comp -L DRAM:4164 IC4 +L AcornElectron:4164 IC4 U 1 1 61D7F23A P 2350 2650 F 0 "IC4" H 2350 3225 50 0000 C CNN @@ -26,7 +26,7 @@ 1 0 0 -1 $EndComp $Comp -L DRAM:4164 IC5 +L AcornElectron:4164 IC5 U 1 1 61D7F241 P 3750 2650 F 0 "IC5" H 3750 3225 50 0000 C CNN @@ -37,7 +37,7 @@ 1 0 0 -1 $EndComp $Comp -L DRAM:4164 IC6 +L AcornElectron:4164 IC6 U 1 1 61D7F248 P 5150 2650 F 0 "IC6" H 5150 3225 50 0000 C CNN @@ -48,7 +48,7 @@ 1 0 0 -1 $EndComp $Comp -L DRAM:4164 IC7 +L AcornElectron:4164 IC7 U 1 1 61D7F24F P 6550 2650 F 0 "IC7" H 6550 3225 50 0000 C CNN @@ -526,6 +526,148 @@ Wire Wire Line 2900 1900 4300 1900 Connection ~ 4300 1900 +$Comp +L AcornElectron:TM4164EA4 IC20 +U 1 1 623B101C +P 1350 5250 +AR Path="/623B101C" Ref="IC20" Part="1" +AR Path="/61D7EEE8/623B101C" Ref="IC20" Part="1" +F 0 "IC20" H 1072 5296 50 0000 R CNN +F 1 "TM4164EA4" H 1072 5205 50 0000 R CNN +F 2 "" H 1400 5750 50 0001 C CNN +F 3 "" H 1400 5750 50 0001 C CNN + 1 1350 5250 + 1 0 0 -1 +$EndComp +Text GLabel 1350 3900 1 50 Input ~ 0 +5V +Text GLabel 1350 6600 3 50 Input ~ 0 +0V +Wire Wire Line + 1350 3900 1350 4000 +Wire Wire Line + 1350 6600 1350 6500 +Text GLabel 7700 5000 2 50 Input ~ 0 +RA[0..7] +Wire Bus Line + 7700 5000 2100 5000 +Entry Wire Line + 2000 5100 2100 5000 +Entry Wire Line + 2000 5200 2100 5100 +Entry Wire Line + 2000 5300 2100 5200 +Entry Wire Line + 2000 5400 2100 5300 +Entry Wire Line + 2000 5500 2100 5400 +Entry Wire Line + 2000 5600 2100 5500 +Entry Wire Line + 2000 5700 2100 5600 +Entry Wire Line + 2000 5800 2100 5700 +Wire Wire Line + 1700 5100 2000 5100 +Wire Wire Line + 1700 5200 2000 5200 +Wire Wire Line + 1700 5300 2000 5300 +Wire Wire Line + 1700 5400 2000 5400 +Wire Wire Line + 1700 5500 2000 5500 +Wire Wire Line + 1700 5600 2000 5600 +Wire Wire Line + 1700 5700 2000 5700 +Wire Wire Line + 1700 5800 2000 5800 +NoConn ~ 1700 5900 +Text Label 1750 5100 0 50 ~ 0 +A0 +Text Label 1750 5200 0 50 ~ 0 +A1 +Text Label 1750 5300 0 50 ~ 0 +A2 +Text Label 1750 5400 0 50 ~ 0 +A3 +Text Label 1750 5500 0 50 ~ 0 +A4 +Text Label 1750 5600 0 50 ~ 0 +A5 +Text Label 1750 5700 0 50 ~ 0 +A6 +Text Label 1750 5800 0 50 ~ 0 +A7 +Text GLabel 7700 4100 2 50 BiDi ~ 0 +RAM[0..3] +Wire Bus Line + 7700 4100 2100 4100 +Entry Wire Line + 2000 4200 2100 4100 +Entry Wire Line + 2000 4300 2100 4200 +Entry Wire Line + 2000 4400 2100 4300 +Entry Wire Line + 2000 4500 2100 4400 +Entry Wire Line + 2000 4600 2100 4500 +Entry Wire Line + 2000 4700 2100 4600 +Entry Wire Line + 2000 4800 2100 4700 +Entry Wire Line + 2000 4900 2100 4800 +Wire Wire Line + 1700 4200 2000 4200 +Wire Wire Line + 1700 4300 2000 4300 +Wire Wire Line + 1700 4400 2000 4400 +Wire Wire Line + 1700 4500 2000 4500 +Wire Wire Line + 1700 4600 2000 4600 +Wire Wire Line + 1700 4700 2000 4700 +Wire Wire Line + 1700 4800 2000 4800 +Wire Wire Line + 1700 4900 2000 4900 +Text Label 1750 4200 0 50 ~ 0 +RAM0 +Text Label 1750 4400 0 50 ~ 0 +RAM1 +Text Label 1750 4600 0 50 ~ 0 +RAM2 +Text Label 1750 4800 0 50 ~ 0 +RAM3 +Text Label 1750 4300 0 50 ~ 0 +RAM0 +Text Label 1750 4500 0 50 ~ 0 +RAM1 +Text Label 1750 4700 0 50 ~ 0 +RAM2 +Text Label 1750 4900 0 50 ~ 0 +RAM3 +Text Label 7600 5000 2 50 ~ 0 +A[0..7] +Text GLabel 7700 6100 2 50 Input ~ 0 +~CAS +Text GLabel 8000 6200 2 50 Input ~ 0 +~RAS +Text GLabel 7700 6300 2 50 Input ~ 0 +~WE +Wire Wire Line + 7700 6100 1700 6100 +Wire Wire Line + 1700 6200 8000 6200 +Wire Wire Line + 1700 6300 7700 6300 +Text Notes 2100 4000 0 50 ~ 0 +Alternative DRAM single-in-line package Wire Wire Line 1900 3100 3300 3100 Wire Wire Line @@ -549,5 +691,9 @@ Wire Bus Line 3000 2700 3000 3300 Wire Bus Line + 2100 5000 2100 5700 +Wire Bus Line + 2100 4100 2100 4800 +Wire Bus Line 1600 1600 7700 1600 $EndSCHEMATC