paul@35 | 1 | Introduction
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paul@35 | 2 | ------------
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paul@35 | 3 |
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paul@35 | 4 | The ArduinoAm29F010 project provides software and a circuit to program
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paul@35 | 5 | Am29F010 flash memory devices using an Arduino board (tested with the Arduino
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paul@35 | 6 | Duemilanove, but likely to work with the Arduino Uno and directly-related
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paul@35 | 7 | boards). In addition, guidance about the use of such flash memory devices is
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paul@36 | 8 | provided for use with microcomputer systems, such as the Acorn Electron and
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paul@36 | 9 | BBC Microcomputer range.
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paul@35 | 10 |
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paul@6 | 11 | The Am29F010-90PC product has been used to test the software and hardware
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paul@35 | 12 | design described here. The PDIP variant of the device, as opposed to the
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paul@35 | 13 | various other packages employed in the product range, is the variant most
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paul@35 | 14 | suitable for use with the Arduino.
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paul@35 | 15 |
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paul@36 | 16 | It is attractive to try and use such flash memory devices as an alternative to
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paul@36 | 17 | EPROM devices, mostly for the practicality and increased convenience involved
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paul@36 | 18 | in programming them, needing only a suitably-wired circuit and conventional
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paul@36 | 19 | microcomputer/microcontroller voltage levels. It is also interesting to try
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paul@36 | 20 | and make the extra space provided by such devices available to the systems in
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paul@36 | 21 | which they will be deployed.
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paul@36 | 22 |
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paul@35 | 23 | Contact, Copyright and Licence Information
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paul@35 | 24 | ------------------------------------------
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paul@35 | 25 |
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paul@35 | 26 | The author can be contacted at the following e-mail address:
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paul@35 | 27 |
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paul@35 | 28 | paul@boddie.org.uk
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paul@35 | 29 |
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paul@35 | 30 | Copyright and licence information can be found in the docs directory - see
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paul@35 | 31 | docs/COPYING.txt and docs/gpl-3.0.txt for more information.
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paul@35 | 32 |
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paul@35 | 33 |
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paul@6 | 34 |
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paul@25 | 35 | Using the Software
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paul@25 | 36 | ==================
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paul@25 | 37 |
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paul@25 | 38 | First of all, to use the Arduino-based programming solution, the Arduino needs
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paul@25 | 39 | to have a program transferred to it. The program is compiled using the
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paul@25 | 40 | Makefile provided, using the simple command...
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paul@25 | 41 |
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paul@25 | 42 | make
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paul@25 | 43 |
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paul@25 | 44 | To upload the program, the "upload" target is used as follows:
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paul@25 | 45 |
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paul@25 | 46 | make upload
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paul@25 | 47 |
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paul@25 | 48 | It is likely that this will fail unless appropriate permissions are available
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paul@25 | 49 | on the device through which the Arduino is accessed on the host machine. Thus,
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paul@25 | 50 | a privileged invocation is likely to be necessary:
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paul@25 | 51 |
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paul@25 | 52 | sudo make upload
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paul@25 | 53 |
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paul@26 | 54 | Testing the Program
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paul@26 | 55 | -------------------
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paul@26 | 56 |
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paul@25 | 57 | With the program uploaded, it should now be possible to communicate with the
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paul@25 | 58 | Arduino. Unless the programming circuit has been constructed, however, there
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paul@25 | 59 | will not be any effect of communicating with the Arduino, other than to check
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paul@25 | 60 | that the program is operational. Running the upload.py script as follows will
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paul@25 | 61 | permit such a test:
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paul@25 | 62 |
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paul@25 | 63 | ./upload.py -i
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paul@25 | 64 |
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paul@25 | 65 | Again, it is likely that this will need to be run in a privileged fashion as
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paul@25 | 66 | follows:
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paul@25 | 67 |
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paul@25 | 68 | sudo ./upload.py -i
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paul@25 | 69 |
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paul@25 | 70 | The script should act as a terminal, showing a ">" prompt that can accept
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paul@25 | 71 | various commands. Merely getting the prompt should be enough of an indication
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paul@25 | 72 | that the program is functioning on the device.
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paul@25 | 73 |
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paul@26 | 74 | Issuing read commands permits the testing of addresses in the device:
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paul@26 | 75 |
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paul@28 | 76 | location sector
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paul@32 | 77 | R00000 0x0000 0 (the first location in the device)
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paul@32 | 78 | R07fff 0x7fff 1 (the final location in sector 1)
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paul@28 | 79 | R10000 0x10000 4 (the first location in sector 4)
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paul@28 | 80 | R1ffff 0x1ffff 7 (the final location in the device)
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paul@26 | 81 |
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paul@26 | 82 | Uploading and Testing Images
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paul@26 | 83 | ----------------------------
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paul@26 | 84 |
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paul@25 | 85 | Once the programming circuit has been constructed (see "Arduino Interfacing"
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paul@25 | 86 | below), the upload.py script can be used to upload data to the Am29F010
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paul@25 | 87 | device. For example:
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paul@25 | 88 |
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paul@25 | 89 | sudo ./upload.py jungle.rom
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paul@25 | 90 |
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paul@25 | 91 | This will take jungle.rom and write it to the first sector of the Am29F010. To
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paul@25 | 92 | verify the operation, the following command can be used:
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paul@25 | 93 |
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paul@25 | 94 | sudo ./upload.py -v jungle.rom
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paul@25 | 95 |
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paul@25 | 96 | To write to other sectors, an option can be specified. For example:
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paul@25 | 97 |
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paul@25 | 98 | sudo ./upload.py -s 1 junglecode.rom
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paul@25 | 99 |
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paul@25 | 100 | Again, the operation can be verified as follows:
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paul@25 | 101 |
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paul@25 | 102 | sudo ./upload.py -s 1 -v junglecode.rom
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paul@25 | 103 |
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paul@25 | 104 | Note that the -s option must appear first.
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paul@25 | 105 |
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paul@25 | 106 | The upload.py script can accept multiple files and will write each of them to
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paul@25 | 107 | consecutive sectors. However, it can be more prudent to write files
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paul@25 | 108 | individually, especially if the circuit is behaving in a less than completely
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paul@25 | 109 | reliable fashion.
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paul@25 | 110 |
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paul@26 | 111 | A Note on Sectors
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paul@26 | 112 | -----------------
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paul@26 | 113 |
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paul@26 | 114 | Each sector is 16 kilobytes long, which corresponds to a 14-bit address range
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paul@28 | 115 | (0x0000 to 0x3FFF). The Arduino interface described below supports 17-bit
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paul@28 | 116 | addressing (A0...A16), permitting access to eight sectors (at 0x0000, 0x4000,
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paul@28 | 117 | 0x8000, 0xC000, 0x10000, 0x14000, 0x18000 and 0x1C000). The simple mapping from
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paul@28 | 118 | a ROM cartridge to the device leaves A16 grounded and thus unable to access the
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paul@28 | 119 | upper four sectors in the device. However, A16 could be connected to VCC to
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paul@28 | 120 | access the upper four sectors.
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paul@26 | 121 |
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paul@34 | 122 |
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paul@34 | 123 |
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paul@34 | 124 | Making a Printed Circuit Board
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paul@34 | 125 | ==============================
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paul@34 | 126 |
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paul@34 | 127 | The pcb directory contains resources for making a PCB with the Fritzing
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paul@34 | 128 | software. In order to track changes in these resources, they have been
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paul@34 | 129 | unpacked from a file saved by Fritzing, and so must be packed together into
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paul@34 | 130 | such a file before being given to Fritzing. This can be done using a script
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paul@34 | 131 | provided:
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paul@34 | 132 |
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paul@34 | 133 | ./make_pcb.sh
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paul@34 | 134 |
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paul@34 | 135 | This will produce a file called ArduinoAm29F010-arduinouno.fzz containing the
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paul@34 | 136 | resources in a zip archive as Fritzing expects.
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paul@34 | 137 |
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paul@35 | 138 | This PCB is featured as a project on the Fritzing Web site:
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paul@35 | 139 |
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paul@35 | 140 | http://fritzing.org/projects/arduino-am29f010-programming-shield
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paul@35 | 141 |
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paul@34 | 142 |
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paul@34 | 143 |
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paul@17 | 144 | Device Compatibility
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paul@17 | 145 | ====================
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paul@17 | 146 |
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paul@17 | 147 | For use with an Acorn Electron ROM cartridge or other board providing a ROM
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paul@17 | 148 | socket, the compatibility of the Am29F010 needs to be assessed in the context
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paul@17 | 149 | of the ROM sockets likely to be provided.
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paul@17 | 150 |
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paul@17 | 151 | Original ROM Pinout Am29F010 Pinout
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paul@17 | 152 | ------------------- ---------------
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paul@17 | 153 |
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paul@17 | 154 | 1 \/ 32 VCC
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paul@17 | 155 | A16 2 31 WE#
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paul@17 | 156 | 1 \/ 28 VCC A15 3 30
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paul@17 | 157 | A12 2 27 A14 A12 4 29 A14
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paul@17 | 158 | A7 3 26 A13 A7 5 28 A13
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paul@17 | 159 | A6 4 25 A8 A6 6 27 A8
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paul@17 | 160 | A5 5 24 A9 A5 7 26 A9
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paul@17 | 161 | A4 6 23 A11 A4 8 25 A11
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paul@17 | 162 | A3 7 22 OE# A3 9 24 OE#
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paul@17 | 163 | A2 8 21 A10 A2 10 23 A10
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paul@17 | 164 | A1 9 20 CS# A1 11 22 CE#
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paul@17 | 165 | A0 10 19 D7 A0 12 21 DQ7
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paul@17 | 166 | D0 11 18 D6 DQ0 13 20 DQ6
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paul@17 | 167 | D1 12 17 D5 DQ1 14 19 DQ5
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paul@17 | 168 | D2 13 16 D4 DQ2 15 18 DQ4
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paul@17 | 169 | GND 14 15 D3 GND/VSS 16 17 DQ3
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paul@17 | 170 |
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paul@17 | 171 | Superimposing the Am29F010 onto a ROM socket would provide compatibility for
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paul@17 | 172 | all pins from A12 to GND/VSS and from A14 to D3/DQ3.
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paul@17 | 173 |
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paul@17 | 174 | Pin 1 in a ROM socket would correspond to A15 but is not necessarily
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paul@17 | 175 | connected, nor, perhaps, is A14 since only 14 bits are required to address 16
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paul@17 | 176 | kilobytes, although there may be 32 kilobyte sockets connecting A14 and using
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paul@20 | 177 | 15 bits to address 32K. A16 and A15 would probably be connected to ground to
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paul@20 | 178 | ensure correct operation, but could also be wired to a selection mechanism so
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paul@20 | 179 | that the entire contents of the flash memory might be exposed.
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paul@17 | 180 |
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paul@36 | 181 | Pin 28 in a ROM socket would provide power, but the corresponding pin 30 on an
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paul@17 | 182 | Am29F010 is not connected. Thus pin 30 would need routing to pin 32 for the
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paul@17 | 183 | flash device socket.
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paul@17 | 184 |
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paul@17 | 185 | Pin 31 for the Am29F010 would need to be asserted. Thus pin 30 might also be
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paul@17 | 186 | routed to pin 31, so that the device would remain read-only at all times.
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paul@17 | 187 |
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paul@20 | 188 | Dual ROM Adapter Usage
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paul@20 | 189 | ======================
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paul@20 | 190 |
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paul@20 | 191 | A single Am29F010 device could be wired to two ROM sockets in order to provide
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paul@20 | 192 | data to both. The above wiring guide would be employed, with connections from
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paul@20 | 193 | both sockets being connected to the Am29F010, but additional logic would be
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paul@20 | 194 | required for the CS# signals originating from the sockets in order to expose
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paul@20 | 195 | the appropriate region of flash memory. ROM #1 would be served by a "lower"
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paul@20 | 196 | 16K region; ROM #2 would be served by an "upper" 16K region; A14 would be used
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paul@20 | 197 | to switch between these regions.
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paul@20 | 198 |
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paul@20 | 199 | When ROM #1's CS# signal is low, an attempt to read from ROM #1 would be
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paul@20 | 200 | occurring, and thus A14 would be held low. And when ROM #2's CS# signal is
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paul@20 | 201 | low, an attempt to read from ROM #2 would be occurring, and thus A14 would be
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paul@20 | 202 | held high.
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paul@20 | 203 |
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paul@22 | 204 | Meanwhile, the CS# signal for the two ROM sockets would need to be combined to
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paul@22 | 205 | produce a resultant CE# signal for the Am29F010.
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paul@22 | 206 |
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paul@22 | 207 | ROM #1 CS# ROM #2 CS# Am29F010 A14 Am29F010 CE#
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paul@22 | 208 | ---------- ---------- ------------ ------------
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paul@22 | 209 | 0 0 Not defined Not defined
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paul@22 | 210 | 0 1 0 0
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paul@22 | 211 | 1 0 1 0
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paul@22 | 212 | 1 1 Not defined 1
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paul@20 | 213 |
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paul@22 | 214 | It might therefore be possible to connect A14 to ROM #1's CS# signal. And the
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paul@22 | 215 | resultant CE# signal could be the product of an AND gate:
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paul@22 | 216 |
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paul@22 | 217 | Am29F010 CE# = ROM #1 CS# AND ROM #2 CS#
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paul@22 | 218 |
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paul@25 | 219 | Wiring Details
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paul@25 | 220 | --------------
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paul@25 | 221 |
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paul@22 | 222 | ROM #1 ROM #2 74HC08 Am29F010
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paul@22 | 223 | ------ ------ ------ --------
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paul@22 | 224 | CS# 1A A14
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paul@22 | 225 | CS# 1B
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paul@22 | 226 | 1Y CE#
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paul@25 | 227 | OE# OE#
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paul@0 | 228 |
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paul@25 | 229 | ROM (Common) 74HC08 Am29F010
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paul@25 | 230 | ------------ ------ --------
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paul@25 | 231 | VCC VCC
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paul@25 | 232 | GND GND
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paul@25 | 233 | VCC VCC
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paul@25 | 234 | VCC WE#
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paul@25 | 235 | D0 DQ0
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paul@25 | 236 | D1 DQ1
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paul@25 | 237 | D2 DQ2
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paul@25 | 238 | D3 DQ3
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paul@25 | 239 | D4 DQ4
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paul@25 | 240 | D5 DQ5
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paul@25 | 241 | D6 DQ6
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paul@25 | 242 | D7 DQ7
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paul@25 | 243 | A0 A0
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paul@25 | 244 | A1 A1
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paul@25 | 245 | A2 A2
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paul@25 | 246 | A3 A3
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paul@25 | 247 | A4 A4
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paul@25 | 248 | A5 A5
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paul@25 | 249 | A6 A6
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paul@25 | 250 | A7 A7
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paul@25 | 251 | A8 A8
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paul@25 | 252 | A9 A9
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paul@25 | 253 | A10 A10
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paul@25 | 254 | A11 A11
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paul@25 | 255 | A12 A12
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paul@25 | 256 | A13 A13
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paul@25 | 257 | GND A15
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paul@25 | 258 | GND A16
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paul@25 | 259 | GND GND
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paul@0 | 260 |
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paul@26 | 261 | Note that A15 and A16 are left grounded, effectively exposing only the first
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paul@26 | 262 | two sectors of the device. By connecting either or both of these to VCC, other
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paul@26 | 263 | pairs of sectors can be manually selected. A mechanism could also be devised
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paul@26 | 264 | to allow selection using logic, but this is not explored here.
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paul@26 | 265 |
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paul@34 | 266 |
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paul@34 | 267 |
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paul@0 | 268 | Arduino Interfacing
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paul@0 | 269 | ===================
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paul@0 | 270 |
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paul@28 | 271 | Arduino can employ at most 14 digital pins (plus 5 switchable analogue pins),
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paul@28 | 272 | whereas the Am29F010B requires 17 address pins, 8 data pins, plus 3 control
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paul@28 | 273 | pins to be utilised.
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paul@0 | 274 |
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paul@0 | 275 | One solution is to map the 3 control pins directly to the Arduino, then to
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paul@28 | 276 | channel address and data via 8 common pins to latches, and then employ two
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paul@28 | 277 | remaining pins to control the latches. When neither latch is selected, the
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paul@28 | 278 | data pins will be used to read or write data from the flash memory.
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paul@0 | 279 |
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paul@28 | 280 | In this scheme, A16 must be directly controlled by an additional pin, separate
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paul@28 | 281 | from the latch-based mechanism. As a result, only 14 pins are needed on the
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paul@28 | 282 | Arduino.
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paul@0 | 283 |
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paul@21 | 284 | 74HC273 Pinout
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paul@21 | 285 | --------------
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paul@21 | 286 |
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paul@21 | 287 | MR# 1 \/ 20 VCC
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paul@21 | 288 | Q0 2 19 Q7
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paul@21 | 289 | D0 3 18 D7
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paul@21 | 290 | D1 4 17 D6
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paul@21 | 291 | Q1 5 16 Q6
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paul@21 | 292 | Q2 6 15 Q5
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paul@21 | 293 | D2 7 14 D5
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paul@21 | 294 | D3 8 13 D4
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paul@21 | 295 | Q3 9 12 Q4
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paul@21 | 296 | GND 10 11 CP
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paul@21 | 297 |
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paul@3 | 298 | Arduino 74HC273 #1 74HC273 #2 Am29F010
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paul@3 | 299 | ------- ---------- ---------- --------
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paul@5 | 300 | A5 CE#
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paul@14 | 301 | A4 OE#
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paul@14 | 302 | A3 WE#
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paul@14 | 303 | 2 CP
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paul@14 | 304 | 3 CP
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paul@27 | 305 | 4 D3 D3 DQ3
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paul@27 | 306 | 5 D2 D2 DQ2
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paul@27 | 307 | 6 D1 D1 DQ1
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paul@27 | 308 | 7 D0 D0 DQ0
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paul@17 | 309 | 8 D4 D4 DQ4
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paul@17 | 310 | 9 D5 D5 DQ5
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paul@17 | 311 | 10 D6 D6 DQ6
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paul@17 | 312 | 11 D7 D7 DQ7
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paul@2 | 313 | Q0 A0
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paul@2 | 314 | Q1 A1
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paul@2 | 315 | Q2 A2
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paul@2 | 316 | Q3 A3
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paul@2 | 317 | Q4 A4
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paul@2 | 318 | Q5 A5
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paul@2 | 319 | Q6 A6
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paul@2 | 320 | Q7 A7
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paul@2 | 321 | Q0 A8
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paul@2 | 322 | Q1 A9
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paul@2 | 323 | Q2 A10
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paul@2 | 324 | Q3 A11
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paul@2 | 325 | Q4 A12
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paul@2 | 326 | Q5 A13
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paul@2 | 327 | Q6 A14
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paul@2 | 328 | Q7 A15
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paul@28 | 329 | A2 A16
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paul@17 | 330 | 5V MR# MR#
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paul@2 | 331 | 5V VCC VCC VCC
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paul@2 | 332 | GND GND GND VSS
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paul@0 | 333 |
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paul@0 | 334 | Set Address
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paul@0 | 335 | -----------
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paul@0 | 336 |
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paul@2 | 337 | 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
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paul@2 | 338 | 74HC273 #1 D[7...0] = A[7...0]
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paul@2 | 339 | 74HC273 #1 CP = 0; 74HC273 #2 CP = 1
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paul@2 | 340 | 74HC273 #2 D[7...0] = A[15...8]
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paul@28 | 341 | Am29F010 A16 = A[16]
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paul@0 | 342 |
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paul@0 | 343 | Write Data
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paul@0 | 344 | ----------
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paul@0 | 345 |
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paul@0 | 346 | Configure pins as D[7...0]
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paul@2 | 347 | WE# = 0
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paul@2 | 348 | 74HC273 #1 CP = 0; 74HC273 #2 CP = 0
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paul@2 | 349 | 74HC273 #3 D[7...0] = D[7...0]
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paul@2 | 350 | WE# = 1
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paul@0 | 351 |
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paul@0 | 352 | Read Data
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paul@0 | 353 | ---------
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paul@0 | 354 |
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paul@0 | 355 | Configure pins as Q[7...0]
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paul@2 | 356 | OE# = 0
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paul@2 | 357 | 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
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paul@2 | 358 | Q[7...0] = 74HC273 #0 Q[7...0]
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paul@2 | 359 | OE# = 1
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paul@25 | 360 |
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paul@25 | 361 | Pins
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paul@25 | 362 | ====
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paul@25 | 363 |
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paul@25 | 364 | A0-A16 17-bit addressing
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paul@25 | 365 | DQ0-DQ7 8-bit data transfer
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paul@25 | 366 | CE# chip enable
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paul@25 | 367 | OE# output enable
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paul@25 | 368 | WE# write enable
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paul@25 | 369 | VCC 5V
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paul@25 | 370 | VSS ground
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paul@25 | 371 | NC (not connected)
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paul@25 | 372 |
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paul@34 | 373 |
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paul@34 | 374 |
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paul@34 | 375 | Technical Notes
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paul@34 | 376 | ===============
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paul@34 | 377 |
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paul@36 | 378 | Information about the operation of the Am29F010 device can be gained from a
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paul@36 | 379 | perusal of the datasheet, and a summary of some of the pertinent details can
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paul@36 | 380 | be found below.
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paul@36 | 381 |
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paul@25 | 382 | Low-Level Operations
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paul@34 | 383 | --------------------
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paul@25 | 384 |
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paul@25 | 385 | CE# high standby
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paul@25 | 386 | CE# low read, write or output disable
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paul@25 | 387 |
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paul@25 | 388 | OE# high, WE# high output disable
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paul@25 | 389 | OE# low, WE# high read
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paul@25 | 390 | OE# high, WE# low write
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paul@25 | 391 |
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paul@25 | 392 | Thus, for reading and writing:
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paul@25 | 393 |
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paul@25 | 394 | OE# = not WE#
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paul@25 | 395 |
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paul@25 | 396 | Timing
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paul@34 | 397 | ------
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paul@25 | 398 |
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paul@25 | 399 | According to the datasheet, addresses are latched on the falling edge of the
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paul@25 | 400 | latest of WE# and CE#, data is latched on the rising edge of the latest of WE#
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paul@25 | 401 | and CE#.
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paul@25 | 402 |
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paul@25 | 403 | Strategy:
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paul@25 | 404 |
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paul@25 | 405 | 1. Start with CE#, OE#, WE# high (standby, output disable)
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paul@25 | 406 | 2. Bring CE# low (output disable)
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paul@25 | 407 | 3. Set addresses
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paul@25 | 408 | 4. Bring WE# or OE# low for operation (write or read)
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paul@25 | 409 | 5. Read or write data
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paul@25 | 410 | 6. Bring WE# or OE# high (output disable)
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paul@25 | 411 |
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paul@25 | 412 | Operation Modes
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paul@34 | 413 | ---------------
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paul@25 | 414 |
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paul@25 | 415 | By default, the device is in read mode, meaning that merely bringing OE# low
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paul@25 | 416 | will produce data for the asserted address.
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paul@25 | 417 |
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paul@25 | 418 | To issue commands to change the mode involves write operations with specific
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paul@25 | 419 | address and data arguments.
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paul@25 | 420 |
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paul@25 | 421 | Sectors
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paul@34 | 422 | --------
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paul@25 | 423 |
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paul@25 | 424 | A[16...14] selects each 16KB sector and is referred to as the sector address
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paul@25 | 425 | or SA in the documentation.
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paul@25 | 426 |
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paul@25 | 427 | Commands
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paul@34 | 428 | --------
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paul@25 | 429 |
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paul@25 | 430 | Reset (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$F0)
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paul@25 | 431 |
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paul@25 | 432 | Autoselect (manufacturer) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
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paul@25 | 433 | (A=$X00; read)
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paul@25 | 434 | => D=$01
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paul@25 | 435 |
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paul@25 | 436 | Autoselect (device) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
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paul@25 | 437 | (A=$X01; read)
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paul@25 | 438 | => D=$20
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paul@25 | 439 |
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paul@25 | 440 | Simple reset (A=$XXXX; D=$F0)
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paul@25 | 441 |
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paul@25 | 442 | Sector erase (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$80);
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paul@25 | 443 | (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=SA; D=$30)
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paul@25 | 444 |
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paul@25 | 445 | Program (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$A0);
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paul@25 | 446 | (A=PA; D=PD)
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paul@25 | 447 |
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paul@36 | 448 | Note that A16 is held low when issuing the constant addresses in the above
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paul@36 | 449 | commands.
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paul@36 | 450 |
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paul@25 | 451 | Progress
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paul@25 | 452 | --------
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paul@25 | 453 |
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paul@25 | 454 | Programming and erasure commands employ data pins as follows:
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paul@25 | 455 |
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paul@25 | 456 | Programming Erasure
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paul@25 | 457 | DQ7 On completion: DQ7-out On completion: 1
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paul@25 | 458 | DQ6 During: toggling value During: toggling value
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paul@25 | 459 | DQ5 On failure: 1 On failure: 1
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paul@25 | 460 | DQ3 Sector erase begun: 1
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paul@25 | 461 |
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paul@25 | 462 | A read operation is required to obtain these outputs, typically with the same
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paul@36 | 463 | address used to initiate each operation. The algorithm described in the
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paul@36 | 464 | datasheet that tests DQ7 and DQ5 is employed to determine whether an operation
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paul@36 | 465 | has completed. It should be noted that the toggling effect on DQ6 occurs from
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paul@36 | 466 | read to read, not at some particular frequency.
|