paul@0 | 1 | Pins
|
paul@0 | 2 | ====
|
paul@0 | 3 |
|
paul@0 | 4 | A0-A16 17-bit addressing
|
paul@0 | 5 | DQ0-DQ7 8-bit data transfer
|
paul@0 | 6 | CE# chip enable
|
paul@0 | 7 | OE# output enable
|
paul@0 | 8 | WE# write enable
|
paul@0 | 9 | VCC 5V
|
paul@0 | 10 | VSS ground
|
paul@0 | 11 | NC (not connected)
|
paul@0 | 12 |
|
paul@0 | 13 | Low-Level Operations
|
paul@0 | 14 | ====================
|
paul@0 | 15 |
|
paul@0 | 16 | CE# high standby
|
paul@0 | 17 | CE# low read, write or output disable
|
paul@0 | 18 |
|
paul@0 | 19 | OE# high, WE# high output disable
|
paul@0 | 20 | OE# low, WE# high read
|
paul@0 | 21 | OE# high, WE# low write
|
paul@0 | 22 |
|
paul@0 | 23 | Thus, for reading and writing:
|
paul@0 | 24 |
|
paul@0 | 25 | OE# = not WE#
|
paul@0 | 26 |
|
paul@0 | 27 | Timing
|
paul@0 | 28 | ======
|
paul@0 | 29 |
|
paul@0 | 30 | Addresses are latched on the falling edge of the latest of WE# and CE#
|
paul@0 | 31 | Data is latched on the rising edge of the latest of WE# and CE#
|
paul@0 | 32 |
|
paul@0 | 33 | Strategy:
|
paul@0 | 34 |
|
paul@0 | 35 | 1. Start with CE#, OE#, WE# high (standby, output disable)
|
paul@0 | 36 | 2. Bring CE# low (output disable)
|
paul@0 | 37 | 3. Set addresses
|
paul@0 | 38 | 4. Bring WE# or OE# low for operation (write or read)
|
paul@0 | 39 | 5. Read or write data
|
paul@0 | 40 | 6. Bring WE# or OE# high (output disable)
|
paul@0 | 41 |
|
paul@0 | 42 | Operation Modes
|
paul@0 | 43 | ===============
|
paul@0 | 44 |
|
paul@0 | 45 | By default, the device is in read mode, meaning that merely bringing OE# low
|
paul@0 | 46 | will produce data for the asserted address.
|
paul@0 | 47 |
|
paul@0 | 48 | To issue commands to change the mode involves write operations with specific
|
paul@0 | 49 | address and data arguments.
|
paul@0 | 50 |
|
paul@0 | 51 | Sectors
|
paul@0 | 52 | =======
|
paul@0 | 53 |
|
paul@0 | 54 | A[16...14] selects each 16KB sector.
|
paul@0 | 55 |
|
paul@0 | 56 | Commands
|
paul@0 | 57 | ========
|
paul@0 | 58 |
|
paul@3 | 59 | Reset (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$F0)
|
paul@3 | 60 | Autoselect (manufacturer) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90); (A=$X00; read)
|
paul@0 | 61 | => D=$01
|
paul@3 | 62 | Autoselect (device) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90); (A=$X01; read)
|
paul@0 | 63 | => D=$20
|
paul@0 | 64 |
|
paul@0 | 65 | Simple reset (A=$XXX; D=$F0)
|
paul@0 | 66 |
|
paul@0 | 67 | Arduino Interfacing
|
paul@0 | 68 | ===================
|
paul@0 | 69 |
|
paul@0 | 70 | Arduino can employ at most 14 digital pins, whereas the Am29F010B requires 17
|
paul@0 | 71 | address pins, 8 data pins, plus 3 control pins to be utilised.
|
paul@0 | 72 |
|
paul@0 | 73 | One solution is to map the 3 control pins directly to the Arduino, then to
|
paul@0 | 74 | channel address and data via 8 common pins to latches, and then employ the
|
paul@0 | 75 | remaining pins to control the latches.
|
paul@0 | 76 |
|
paul@2 | 77 | Two pins can be used to select the latches, and when neither latch is
|
paul@2 | 78 | selected, the data pins will be used to read or write data from the flash
|
paul@2 | 79 | memory.
|
paul@0 | 80 |
|
paul@0 | 81 | As a result, only 13 pins are needed on the Arduino.
|
paul@0 | 82 |
|
paul@3 | 83 | Arduino 74HC273 #1 74HC273 #2 Am29F010
|
paul@3 | 84 | ------- ---------- ---------- --------
|
paul@2 | 85 | 1 CE#
|
paul@2 | 86 | 2 OE#
|
paul@2 | 87 | 3 WE#
|
paul@2 | 88 | 4 CP
|
paul@2 | 89 | 5 CP
|
paul@2 | 90 | 6 D0 (*) D0 (*) DQ0
|
paul@2 | 91 | 7 D1 (*) D1 (*) DQ1
|
paul@2 | 92 | 8 D2 (*) D2 (*) DQ2
|
paul@2 | 93 | 9 D3 (*) D3 (*) DQ3
|
paul@2 | 94 | 10 D4 (*) D4 (*) DQ4
|
paul@2 | 95 | 11 D5 (*) D5 (*) DQ5
|
paul@2 | 96 | 12 D6 (*) D6 (*) DQ6
|
paul@2 | 97 | 13 D7 (*) D7 (*) DQ7
|
paul@2 | 98 | Q0 A0
|
paul@2 | 99 | Q1 A1
|
paul@2 | 100 | Q2 A2
|
paul@2 | 101 | Q3 A3
|
paul@2 | 102 | Q4 A4
|
paul@2 | 103 | Q5 A5
|
paul@2 | 104 | Q6 A6
|
paul@2 | 105 | Q7 A7
|
paul@2 | 106 | Q0 A8
|
paul@2 | 107 | Q1 A9
|
paul@2 | 108 | Q2 A10
|
paul@2 | 109 | Q3 A11
|
paul@2 | 110 | Q4 A12
|
paul@2 | 111 | Q5 A13
|
paul@2 | 112 | Q6 A14
|
paul@2 | 113 | Q7 A15
|
paul@2 | 114 | GND A16 (not used)
|
paul@2 | 115 | 5V MR# (**) MR# (**)
|
paul@2 | 116 | 5V VCC VCC VCC
|
paul@2 | 117 | GND GND GND VSS
|
paul@0 | 118 |
|
paul@0 | 119 | (*) Apply pull-down resistor to 74HC273 D inputs when driving using switches.
|
paul@0 | 120 | (**) Apply pull-up resistor to 74HC273 MR# inputs to preserve state.
|
paul@0 | 121 |
|
paul@0 | 122 | 74HC273 Q outputs may initially be high and should be reset, either driving
|
paul@0 | 123 | MR# low or by explicitly latching values onto each device.
|
paul@0 | 124 |
|
paul@0 | 125 | Set Address
|
paul@0 | 126 | -----------
|
paul@0 | 127 |
|
paul@2 | 128 | 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
|
paul@2 | 129 | 74HC273 #1 D[7...0] = A[7...0]
|
paul@2 | 130 | 74HC273 #1 CP = 0; 74HC273 #2 CP = 1
|
paul@2 | 131 | 74HC273 #2 D[7...0] = A[15...8]
|
paul@0 | 132 |
|
paul@0 | 133 | Write Data
|
paul@0 | 134 | ----------
|
paul@0 | 135 |
|
paul@0 | 136 | Configure pins as D[7...0]
|
paul@2 | 137 | WE# = 0
|
paul@2 | 138 | 74HC273 #1 CP = 0; 74HC273 #2 CP = 0
|
paul@2 | 139 | 74HC273 #3 D[7...0] = D[7...0]
|
paul@2 | 140 | WE# = 1
|
paul@0 | 141 |
|
paul@0 | 142 | Read Data
|
paul@0 | 143 | ---------
|
paul@0 | 144 |
|
paul@0 | 145 | Configure pins as Q[7...0]
|
paul@2 | 146 | OE# = 0
|
paul@2 | 147 | 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
|
paul@2 | 148 | Q[7...0] = 74HC273 #0 Q[7...0]
|
paul@2 | 149 | OE# = 1
|