paul@6 | 1 | The Am29F010-90PC product has been used to test the software and hardware
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paul@6 | 2 | design described here.
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paul@6 | 3 |
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paul@17 | 4 | Device Compatibility
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paul@17 | 5 | ====================
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paul@17 | 6 |
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paul@17 | 7 | For use with an Acorn Electron ROM cartridge or other board providing a ROM
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paul@17 | 8 | socket, the compatibility of the Am29F010 needs to be assessed in the context
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paul@17 | 9 | of the ROM sockets likely to be provided.
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paul@17 | 10 |
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paul@17 | 11 | Original ROM Pinout Am29F010 Pinout
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paul@17 | 12 | ------------------- ---------------
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paul@17 | 13 |
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paul@17 | 14 | 1 \/ 32 VCC
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paul@17 | 15 | A16 2 31 WE#
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paul@17 | 16 | 1 \/ 28 VCC A15 3 30
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paul@17 | 17 | A12 2 27 A14 A12 4 29 A14
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paul@17 | 18 | A7 3 26 A13 A7 5 28 A13
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paul@17 | 19 | A6 4 25 A8 A6 6 27 A8
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paul@17 | 20 | A5 5 24 A9 A5 7 26 A9
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paul@17 | 21 | A4 6 23 A11 A4 8 25 A11
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paul@17 | 22 | A3 7 22 OE# A3 9 24 OE#
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paul@17 | 23 | A2 8 21 A10 A2 10 23 A10
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paul@17 | 24 | A1 9 20 CS# A1 11 22 CE#
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paul@17 | 25 | A0 10 19 D7 A0 12 21 DQ7
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paul@17 | 26 | D0 11 18 D6 DQ0 13 20 DQ6
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paul@17 | 27 | D1 12 17 D5 DQ1 14 19 DQ5
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paul@17 | 28 | D2 13 16 D4 DQ2 15 18 DQ4
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paul@17 | 29 | GND 14 15 D3 GND/VSS 16 17 DQ3
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paul@17 | 30 |
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paul@17 | 31 | Superimposing the Am29F010 onto a ROM socket would provide compatibility for
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paul@17 | 32 | all pins from A12 to GND/VSS and from A14 to D3/DQ3.
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paul@17 | 33 |
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paul@17 | 34 | Pin 1 in a ROM socket would correspond to A15 but is not necessarily
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paul@17 | 35 | connected, nor, perhaps, is A14 since only 14 bits are required to address 16
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paul@17 | 36 | kilobytes, although there may be 32 kilobyte sockets connecting A14 and using
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paul@20 | 37 | 15 bits to address 32K. A16 and A15 would probably be connected to ground to
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paul@20 | 38 | ensure correct operation, but could also be wired to a selection mechanism so
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paul@20 | 39 | that the entire contents of the flash memory might be exposed.
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paul@17 | 40 |
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paul@17 | 41 | Pin 28 is a ROM socket would provide power, but the corresponding pin 30 on an
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paul@17 | 42 | Am29F010 is not connected. Thus pin 30 would need routing to pin 32 for the
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paul@17 | 43 | flash device socket.
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paul@17 | 44 |
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paul@17 | 45 | Pin 31 for the Am29F010 would need to be asserted. Thus pin 30 might also be
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paul@17 | 46 | routed to pin 31, so that the device would remain read-only at all times.
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paul@17 | 47 |
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paul@20 | 48 | Dual ROM Adapter Usage
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paul@20 | 49 | ======================
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paul@20 | 50 |
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paul@20 | 51 | A single Am29F010 device could be wired to two ROM sockets in order to provide
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paul@20 | 52 | data to both. The above wiring guide would be employed, with connections from
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paul@20 | 53 | both sockets being connected to the Am29F010, but additional logic would be
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paul@20 | 54 | required for the CS# signals originating from the sockets in order to expose
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paul@20 | 55 | the appropriate region of flash memory. ROM #1 would be served by a "lower"
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paul@20 | 56 | 16K region; ROM #2 would be served by an "upper" 16K region; A14 would be used
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paul@20 | 57 | to switch between these regions.
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paul@20 | 58 |
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paul@20 | 59 | When ROM #1's CS# signal is low, an attempt to read from ROM #1 would be
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paul@20 | 60 | occurring, and thus A14 would be held low. And when ROM #2's CS# signal is
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paul@20 | 61 | low, an attempt to read from ROM #2 would be occurring, and thus A14 would be
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paul@20 | 62 | held high.
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paul@20 | 63 |
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paul@20 | 64 | ROM #1 CS# ROM #2 CS# Am29F010 A14
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paul@20 | 65 | ---------- ---------- ------------
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paul@20 | 66 | 0 0 Not defined
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paul@20 | 67 | 0 1 0
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paul@20 | 68 | 1 0 1
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paul@20 | 69 | 1 1 Not defined
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paul@20 | 70 |
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paul@20 | 71 | It might therefore be possible to connect A14 to ROM #1's CS# signal.
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paul@20 | 72 |
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paul@0 | 73 | Pins
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paul@0 | 74 | ====
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paul@0 | 75 |
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paul@0 | 76 | A0-A16 17-bit addressing
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paul@0 | 77 | DQ0-DQ7 8-bit data transfer
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paul@0 | 78 | CE# chip enable
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paul@0 | 79 | OE# output enable
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paul@0 | 80 | WE# write enable
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paul@0 | 81 | VCC 5V
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paul@0 | 82 | VSS ground
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paul@0 | 83 | NC (not connected)
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paul@0 | 84 |
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paul@0 | 85 | Low-Level Operations
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paul@0 | 86 | ====================
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paul@0 | 87 |
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paul@0 | 88 | CE# high standby
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paul@0 | 89 | CE# low read, write or output disable
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paul@0 | 90 |
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paul@0 | 91 | OE# high, WE# high output disable
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paul@0 | 92 | OE# low, WE# high read
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paul@0 | 93 | OE# high, WE# low write
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paul@0 | 94 |
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paul@0 | 95 | Thus, for reading and writing:
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paul@0 | 96 |
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paul@0 | 97 | OE# = not WE#
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paul@0 | 98 |
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paul@0 | 99 | Timing
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paul@0 | 100 | ======
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paul@0 | 101 |
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paul@0 | 102 | Addresses are latched on the falling edge of the latest of WE# and CE#
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paul@0 | 103 | Data is latched on the rising edge of the latest of WE# and CE#
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paul@0 | 104 |
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paul@0 | 105 | Strategy:
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paul@0 | 106 |
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paul@0 | 107 | 1. Start with CE#, OE#, WE# high (standby, output disable)
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paul@0 | 108 | 2. Bring CE# low (output disable)
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paul@0 | 109 | 3. Set addresses
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paul@0 | 110 | 4. Bring WE# or OE# low for operation (write or read)
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paul@0 | 111 | 5. Read or write data
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paul@0 | 112 | 6. Bring WE# or OE# high (output disable)
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paul@0 | 113 |
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paul@0 | 114 | Operation Modes
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paul@0 | 115 | ===============
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paul@0 | 116 |
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paul@0 | 117 | By default, the device is in read mode, meaning that merely bringing OE# low
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paul@0 | 118 | will produce data for the asserted address.
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paul@0 | 119 |
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paul@0 | 120 | To issue commands to change the mode involves write operations with specific
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paul@0 | 121 | address and data arguments.
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paul@0 | 122 |
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paul@0 | 123 | Sectors
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paul@0 | 124 | =======
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paul@0 | 125 |
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paul@6 | 126 | A[16...14] selects each 16KB sector and is referred to as the sector address
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paul@6 | 127 | or SA in the documentation.
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paul@0 | 128 |
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paul@0 | 129 | Commands
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paul@0 | 130 | ========
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paul@0 | 131 |
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paul@3 | 132 | Reset (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$F0)
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paul@6 | 133 |
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paul@6 | 134 | Autoselect (manufacturer) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
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paul@6 | 135 | (A=$X00; read)
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paul@0 | 136 | => D=$01
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paul@6 | 137 |
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paul@6 | 138 | Autoselect (device) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
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paul@6 | 139 | (A=$X01; read)
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paul@0 | 140 | => D=$20
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paul@0 | 141 |
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paul@6 | 142 | Simple reset (A=$XXXX; D=$F0)
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paul@6 | 143 |
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paul@6 | 144 | Sector erase (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$80);
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paul@6 | 145 | (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=SA; D=$30)
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paul@6 | 146 |
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paul@6 | 147 | Program (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$A0);
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paul@6 | 148 | (A=PA; D=PD)
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paul@6 | 149 |
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paul@6 | 150 | Progress
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paul@6 | 151 | --------
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paul@6 | 152 |
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paul@6 | 153 | Programming and erasure commands employ data pins as follows:
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paul@6 | 154 |
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paul@6 | 155 | Programming Erasure
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paul@6 | 156 | DQ7 On completion: DQ7-out On completion: 1
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paul@6 | 157 | DQ6 During: toggling value During: toggling value
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paul@6 | 158 | DQ5 On failure: 1 On failure: 1
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paul@6 | 159 | DQ3 Sector erase begun: 1
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paul@6 | 160 |
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paul@6 | 161 | A read operation is required to obtain these outputs, typically with the same
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paul@6 | 162 | address used to initiate each operation.
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paul@0 | 163 |
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paul@0 | 164 | Arduino Interfacing
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paul@0 | 165 | ===================
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paul@0 | 166 |
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paul@0 | 167 | Arduino can employ at most 14 digital pins, whereas the Am29F010B requires 17
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paul@0 | 168 | address pins, 8 data pins, plus 3 control pins to be utilised.
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paul@0 | 169 |
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paul@0 | 170 | One solution is to map the 3 control pins directly to the Arduino, then to
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paul@0 | 171 | channel address and data via 8 common pins to latches, and then employ the
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paul@0 | 172 | remaining pins to control the latches.
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paul@0 | 173 |
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paul@2 | 174 | Two pins can be used to select the latches, and when neither latch is
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paul@2 | 175 | selected, the data pins will be used to read or write data from the flash
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paul@2 | 176 | memory.
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paul@0 | 177 |
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paul@0 | 178 | As a result, only 13 pins are needed on the Arduino.
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paul@0 | 179 |
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paul@3 | 180 | Arduino 74HC273 #1 74HC273 #2 Am29F010
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paul@3 | 181 | ------- ---------- ---------- --------
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paul@5 | 182 | A5 CE#
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paul@14 | 183 | A4 OE#
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paul@14 | 184 | A3 WE#
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paul@14 | 185 | 2 CP
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paul@14 | 186 | 3 CP
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paul@17 | 187 | 4 D0 D0 DQ0
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paul@17 | 188 | 5 D1 D1 DQ1
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paul@17 | 189 | 6 D2 D2 DQ2
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paul@17 | 190 | 7 D3 D3 DQ3
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paul@17 | 191 | 8 D4 D4 DQ4
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paul@17 | 192 | 9 D5 D5 DQ5
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paul@17 | 193 | 10 D6 D6 DQ6
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paul@17 | 194 | 11 D7 D7 DQ7
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paul@2 | 195 | Q0 A0
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paul@2 | 196 | Q1 A1
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paul@2 | 197 | Q2 A2
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paul@2 | 198 | Q3 A3
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paul@2 | 199 | Q4 A4
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paul@2 | 200 | Q5 A5
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paul@2 | 201 | Q6 A6
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paul@2 | 202 | Q7 A7
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paul@2 | 203 | Q0 A8
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paul@2 | 204 | Q1 A9
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paul@2 | 205 | Q2 A10
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paul@2 | 206 | Q3 A11
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paul@2 | 207 | Q4 A12
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paul@2 | 208 | Q5 A13
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paul@2 | 209 | Q6 A14
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paul@2 | 210 | Q7 A15
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paul@2 | 211 | GND A16 (not used)
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paul@17 | 212 | 5V MR# MR#
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paul@2 | 213 | 5V VCC VCC VCC
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paul@2 | 214 | GND GND GND VSS
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paul@0 | 215 |
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paul@0 | 216 | Set Address
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paul@0 | 217 | -----------
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paul@0 | 218 |
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paul@2 | 219 | 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
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paul@2 | 220 | 74HC273 #1 D[7...0] = A[7...0]
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paul@2 | 221 | 74HC273 #1 CP = 0; 74HC273 #2 CP = 1
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paul@2 | 222 | 74HC273 #2 D[7...0] = A[15...8]
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paul@0 | 223 |
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paul@0 | 224 | Write Data
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paul@0 | 225 | ----------
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paul@0 | 226 |
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paul@0 | 227 | Configure pins as D[7...0]
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paul@2 | 228 | WE# = 0
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paul@2 | 229 | 74HC273 #1 CP = 0; 74HC273 #2 CP = 0
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paul@2 | 230 | 74HC273 #3 D[7...0] = D[7...0]
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paul@2 | 231 | WE# = 1
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paul@0 | 232 |
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paul@0 | 233 | Read Data
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paul@0 | 234 | ---------
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paul@0 | 235 |
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paul@0 | 236 | Configure pins as Q[7...0]
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paul@2 | 237 | OE# = 0
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paul@2 | 238 | 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
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paul@2 | 239 | Q[7...0] = 74HC273 #0 Q[7...0]
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paul@2 | 240 | OE# = 1
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