paul@6 | 1 | The Am29F010-90PC product has been used to test the software and hardware
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paul@6 | 2 | design described here.
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paul@6 | 3 |
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paul@25 | 4 | Using the Software
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paul@25 | 5 | ==================
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paul@25 | 6 |
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paul@25 | 7 | First of all, to use the Arduino-based programming solution, the Arduino needs
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paul@25 | 8 | to have a program transferred to it. The program is compiled using the
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paul@25 | 9 | Makefile provided, using the simple command...
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paul@25 | 10 |
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paul@25 | 11 | make
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paul@25 | 12 |
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paul@25 | 13 | To upload the program, the "upload" target is used as follows:
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paul@25 | 14 |
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paul@25 | 15 | make upload
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paul@25 | 16 |
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paul@25 | 17 | It is likely that this will fail unless appropriate permissions are available
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paul@25 | 18 | on the device through which the Arduino is accessed on the host machine. Thus,
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paul@25 | 19 | a privileged invocation is likely to be necessary:
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paul@25 | 20 |
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paul@25 | 21 | sudo make upload
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paul@25 | 22 |
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paul@26 | 23 | Testing the Program
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paul@26 | 24 | -------------------
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paul@26 | 25 |
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paul@25 | 26 | With the program uploaded, it should now be possible to communicate with the
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paul@25 | 27 | Arduino. Unless the programming circuit has been constructed, however, there
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paul@25 | 28 | will not be any effect of communicating with the Arduino, other than to check
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paul@25 | 29 | that the program is operational. Running the upload.py script as follows will
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paul@25 | 30 | permit such a test:
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paul@25 | 31 |
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paul@25 | 32 | ./upload.py -i
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paul@25 | 33 |
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paul@25 | 34 | Again, it is likely that this will need to be run in a privileged fashion as
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paul@25 | 35 | follows:
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paul@25 | 36 |
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paul@25 | 37 | sudo ./upload.py -i
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paul@25 | 38 |
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paul@25 | 39 | The script should act as a terminal, showing a ">" prompt that can accept
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paul@25 | 40 | various commands. Merely getting the prompt should be enough of an indication
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paul@25 | 41 | that the program is functioning on the device.
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paul@25 | 42 |
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paul@26 | 43 | Issuing read commands permits the testing of addresses in the device:
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paul@26 | 44 |
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paul@28 | 45 | location sector
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paul@32 | 46 | R00000 0x0000 0 (the first location in the device)
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paul@32 | 47 | R07fff 0x7fff 1 (the final location in sector 1)
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paul@28 | 48 | R10000 0x10000 4 (the first location in sector 4)
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paul@28 | 49 | R1ffff 0x1ffff 7 (the final location in the device)
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paul@26 | 50 |
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paul@26 | 51 | Uploading and Testing Images
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paul@26 | 52 | ----------------------------
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paul@26 | 53 |
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paul@25 | 54 | Once the programming circuit has been constructed (see "Arduino Interfacing"
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paul@25 | 55 | below), the upload.py script can be used to upload data to the Am29F010
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paul@25 | 56 | device. For example:
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paul@25 | 57 |
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paul@25 | 58 | sudo ./upload.py jungle.rom
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paul@25 | 59 |
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paul@25 | 60 | This will take jungle.rom and write it to the first sector of the Am29F010. To
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paul@25 | 61 | verify the operation, the following command can be used:
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paul@25 | 62 |
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paul@25 | 63 | sudo ./upload.py -v jungle.rom
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paul@25 | 64 |
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paul@25 | 65 | To write to other sectors, an option can be specified. For example:
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paul@25 | 66 |
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paul@25 | 67 | sudo ./upload.py -s 1 junglecode.rom
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paul@25 | 68 |
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paul@25 | 69 | Again, the operation can be verified as follows:
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paul@25 | 70 |
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paul@25 | 71 | sudo ./upload.py -s 1 -v junglecode.rom
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paul@25 | 72 |
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paul@25 | 73 | Note that the -s option must appear first.
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paul@25 | 74 |
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paul@25 | 75 | The upload.py script can accept multiple files and will write each of them to
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paul@25 | 76 | consecutive sectors. However, it can be more prudent to write files
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paul@25 | 77 | individually, especially if the circuit is behaving in a less than completely
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paul@25 | 78 | reliable fashion.
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paul@25 | 79 |
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paul@26 | 80 | A Note on Sectors
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paul@26 | 81 | -----------------
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paul@26 | 82 |
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paul@26 | 83 | Each sector is 16 kilobytes long, which corresponds to a 14-bit address range
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paul@28 | 84 | (0x0000 to 0x3FFF). The Arduino interface described below supports 17-bit
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paul@28 | 85 | addressing (A0...A16), permitting access to eight sectors (at 0x0000, 0x4000,
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paul@28 | 86 | 0x8000, 0xC000, 0x10000, 0x14000, 0x18000 and 0x1C000). The simple mapping from
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paul@28 | 87 | a ROM cartridge to the device leaves A16 grounded and thus unable to access the
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paul@28 | 88 | upper four sectors in the device. However, A16 could be connected to VCC to
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paul@28 | 89 | access the upper four sectors.
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paul@26 | 90 |
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paul@17 | 91 | Device Compatibility
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paul@17 | 92 | ====================
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paul@17 | 93 |
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paul@17 | 94 | For use with an Acorn Electron ROM cartridge or other board providing a ROM
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paul@17 | 95 | socket, the compatibility of the Am29F010 needs to be assessed in the context
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paul@17 | 96 | of the ROM sockets likely to be provided.
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paul@17 | 97 |
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paul@17 | 98 | Original ROM Pinout Am29F010 Pinout
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paul@17 | 99 | ------------------- ---------------
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paul@17 | 100 |
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paul@17 | 101 | 1 \/ 32 VCC
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paul@17 | 102 | A16 2 31 WE#
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paul@17 | 103 | 1 \/ 28 VCC A15 3 30
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paul@17 | 104 | A12 2 27 A14 A12 4 29 A14
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paul@17 | 105 | A7 3 26 A13 A7 5 28 A13
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paul@17 | 106 | A6 4 25 A8 A6 6 27 A8
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paul@17 | 107 | A5 5 24 A9 A5 7 26 A9
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paul@17 | 108 | A4 6 23 A11 A4 8 25 A11
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paul@17 | 109 | A3 7 22 OE# A3 9 24 OE#
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paul@17 | 110 | A2 8 21 A10 A2 10 23 A10
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paul@17 | 111 | A1 9 20 CS# A1 11 22 CE#
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paul@17 | 112 | A0 10 19 D7 A0 12 21 DQ7
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paul@17 | 113 | D0 11 18 D6 DQ0 13 20 DQ6
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paul@17 | 114 | D1 12 17 D5 DQ1 14 19 DQ5
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paul@17 | 115 | D2 13 16 D4 DQ2 15 18 DQ4
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paul@17 | 116 | GND 14 15 D3 GND/VSS 16 17 DQ3
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paul@17 | 117 |
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paul@17 | 118 | Superimposing the Am29F010 onto a ROM socket would provide compatibility for
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paul@17 | 119 | all pins from A12 to GND/VSS and from A14 to D3/DQ3.
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paul@17 | 120 |
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paul@17 | 121 | Pin 1 in a ROM socket would correspond to A15 but is not necessarily
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paul@17 | 122 | connected, nor, perhaps, is A14 since only 14 bits are required to address 16
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paul@17 | 123 | kilobytes, although there may be 32 kilobyte sockets connecting A14 and using
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paul@20 | 124 | 15 bits to address 32K. A16 and A15 would probably be connected to ground to
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paul@20 | 125 | ensure correct operation, but could also be wired to a selection mechanism so
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paul@20 | 126 | that the entire contents of the flash memory might be exposed.
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paul@17 | 127 |
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paul@17 | 128 | Pin 28 is a ROM socket would provide power, but the corresponding pin 30 on an
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paul@17 | 129 | Am29F010 is not connected. Thus pin 30 would need routing to pin 32 for the
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paul@17 | 130 | flash device socket.
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paul@17 | 131 |
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paul@17 | 132 | Pin 31 for the Am29F010 would need to be asserted. Thus pin 30 might also be
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paul@17 | 133 | routed to pin 31, so that the device would remain read-only at all times.
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paul@17 | 134 |
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paul@20 | 135 | Dual ROM Adapter Usage
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paul@20 | 136 | ======================
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paul@20 | 137 |
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paul@20 | 138 | A single Am29F010 device could be wired to two ROM sockets in order to provide
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paul@20 | 139 | data to both. The above wiring guide would be employed, with connections from
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paul@20 | 140 | both sockets being connected to the Am29F010, but additional logic would be
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paul@20 | 141 | required for the CS# signals originating from the sockets in order to expose
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paul@20 | 142 | the appropriate region of flash memory. ROM #1 would be served by a "lower"
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paul@20 | 143 | 16K region; ROM #2 would be served by an "upper" 16K region; A14 would be used
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paul@20 | 144 | to switch between these regions.
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paul@20 | 145 |
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paul@20 | 146 | When ROM #1's CS# signal is low, an attempt to read from ROM #1 would be
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paul@20 | 147 | occurring, and thus A14 would be held low. And when ROM #2's CS# signal is
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paul@20 | 148 | low, an attempt to read from ROM #2 would be occurring, and thus A14 would be
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paul@20 | 149 | held high.
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paul@20 | 150 |
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paul@22 | 151 | Meanwhile, the CS# signal for the two ROM sockets would need to be combined to
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paul@22 | 152 | produce a resultant CE# signal for the Am29F010.
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paul@22 | 153 |
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paul@22 | 154 | ROM #1 CS# ROM #2 CS# Am29F010 A14 Am29F010 CE#
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paul@22 | 155 | ---------- ---------- ------------ ------------
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paul@22 | 156 | 0 0 Not defined Not defined
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paul@22 | 157 | 0 1 0 0
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paul@22 | 158 | 1 0 1 0
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paul@22 | 159 | 1 1 Not defined 1
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paul@20 | 160 |
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paul@22 | 161 | It might therefore be possible to connect A14 to ROM #1's CS# signal. And the
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paul@22 | 162 | resultant CE# signal could be the product of an AND gate:
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paul@22 | 163 |
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paul@22 | 164 | Am29F010 CE# = ROM #1 CS# AND ROM #2 CS#
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paul@22 | 165 |
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paul@25 | 166 | Wiring Details
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paul@25 | 167 | --------------
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paul@25 | 168 |
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paul@22 | 169 | ROM #1 ROM #2 74HC08 Am29F010
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paul@22 | 170 | ------ ------ ------ --------
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paul@22 | 171 | CS# 1A A14
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paul@22 | 172 | CS# 1B
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paul@22 | 173 | 1Y CE#
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paul@25 | 174 | OE# OE#
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paul@0 | 175 |
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paul@25 | 176 | ROM (Common) 74HC08 Am29F010
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paul@25 | 177 | ------------ ------ --------
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paul@25 | 178 | VCC VCC
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paul@25 | 179 | GND GND
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paul@25 | 180 | VCC VCC
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paul@25 | 181 | VCC WE#
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paul@25 | 182 | D0 DQ0
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paul@25 | 183 | D1 DQ1
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paul@25 | 184 | D2 DQ2
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paul@25 | 185 | D3 DQ3
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paul@25 | 186 | D4 DQ4
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paul@25 | 187 | D5 DQ5
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paul@25 | 188 | D6 DQ6
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paul@25 | 189 | D7 DQ7
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paul@25 | 190 | A0 A0
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paul@25 | 191 | A1 A1
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paul@25 | 192 | A2 A2
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paul@25 | 193 | A3 A3
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paul@25 | 194 | A4 A4
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paul@25 | 195 | A5 A5
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paul@25 | 196 | A6 A6
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paul@25 | 197 | A7 A7
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paul@25 | 198 | A8 A8
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paul@25 | 199 | A9 A9
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paul@25 | 200 | A10 A10
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paul@25 | 201 | A11 A11
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paul@25 | 202 | A12 A12
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paul@25 | 203 | A13 A13
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paul@25 | 204 | GND A15
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paul@25 | 205 | GND A16
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paul@25 | 206 | GND GND
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paul@0 | 207 |
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paul@26 | 208 | Note that A15 and A16 are left grounded, effectively exposing only the first
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paul@26 | 209 | two sectors of the device. By connecting either or both of these to VCC, other
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paul@26 | 210 | pairs of sectors can be manually selected. A mechanism could also be devised
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paul@26 | 211 | to allow selection using logic, but this is not explored here.
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paul@26 | 212 |
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paul@0 | 213 | Arduino Interfacing
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paul@0 | 214 | ===================
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paul@0 | 215 |
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paul@28 | 216 | Arduino can employ at most 14 digital pins (plus 5 switchable analogue pins),
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paul@28 | 217 | whereas the Am29F010B requires 17 address pins, 8 data pins, plus 3 control
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paul@28 | 218 | pins to be utilised.
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paul@0 | 219 |
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paul@0 | 220 | One solution is to map the 3 control pins directly to the Arduino, then to
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paul@28 | 221 | channel address and data via 8 common pins to latches, and then employ two
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paul@28 | 222 | remaining pins to control the latches. When neither latch is selected, the
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paul@28 | 223 | data pins will be used to read or write data from the flash memory.
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paul@0 | 224 |
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paul@28 | 225 | In this scheme, A16 must be directly controlled by an additional pin, separate
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paul@28 | 226 | from the latch-based mechanism. As a result, only 14 pins are needed on the
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paul@28 | 227 | Arduino.
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paul@0 | 228 |
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paul@21 | 229 | 74HC273 Pinout
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paul@21 | 230 | --------------
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paul@21 | 231 |
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paul@21 | 232 | MR# 1 \/ 20 VCC
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paul@21 | 233 | Q0 2 19 Q7
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paul@21 | 234 | D0 3 18 D7
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paul@21 | 235 | D1 4 17 D6
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paul@21 | 236 | Q1 5 16 Q6
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paul@21 | 237 | Q2 6 15 Q5
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paul@21 | 238 | D2 7 14 D5
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paul@21 | 239 | D3 8 13 D4
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paul@21 | 240 | Q3 9 12 Q4
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paul@21 | 241 | GND 10 11 CP
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paul@21 | 242 |
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paul@3 | 243 | Arduino 74HC273 #1 74HC273 #2 Am29F010
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paul@3 | 244 | ------- ---------- ---------- --------
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paul@5 | 245 | A5 CE#
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paul@14 | 246 | A4 OE#
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paul@14 | 247 | A3 WE#
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paul@14 | 248 | 2 CP
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paul@14 | 249 | 3 CP
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paul@27 | 250 | 4 D3 D3 DQ3
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paul@27 | 251 | 5 D2 D2 DQ2
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paul@27 | 252 | 6 D1 D1 DQ1
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paul@27 | 253 | 7 D0 D0 DQ0
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paul@17 | 254 | 8 D4 D4 DQ4
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paul@17 | 255 | 9 D5 D5 DQ5
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paul@17 | 256 | 10 D6 D6 DQ6
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paul@17 | 257 | 11 D7 D7 DQ7
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paul@2 | 258 | Q0 A0
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paul@2 | 259 | Q1 A1
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paul@2 | 260 | Q2 A2
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paul@2 | 261 | Q3 A3
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paul@2 | 262 | Q4 A4
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paul@2 | 263 | Q5 A5
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paul@2 | 264 | Q6 A6
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paul@2 | 265 | Q7 A7
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paul@2 | 266 | Q0 A8
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paul@2 | 267 | Q1 A9
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paul@2 | 268 | Q2 A10
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paul@2 | 269 | Q3 A11
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paul@2 | 270 | Q4 A12
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paul@2 | 271 | Q5 A13
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paul@2 | 272 | Q6 A14
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paul@2 | 273 | Q7 A15
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paul@28 | 274 | A2 A16
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paul@17 | 275 | 5V MR# MR#
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paul@2 | 276 | 5V VCC VCC VCC
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paul@2 | 277 | GND GND GND VSS
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paul@0 | 278 |
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paul@0 | 279 | Set Address
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paul@0 | 280 | -----------
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paul@0 | 281 |
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paul@2 | 282 | 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
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paul@2 | 283 | 74HC273 #1 D[7...0] = A[7...0]
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paul@2 | 284 | 74HC273 #1 CP = 0; 74HC273 #2 CP = 1
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paul@2 | 285 | 74HC273 #2 D[7...0] = A[15...8]
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paul@28 | 286 | Am29F010 A16 = A[16]
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paul@0 | 287 |
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paul@0 | 288 | Write Data
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paul@0 | 289 | ----------
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paul@0 | 290 |
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paul@0 | 291 | Configure pins as D[7...0]
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paul@2 | 292 | WE# = 0
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paul@2 | 293 | 74HC273 #1 CP = 0; 74HC273 #2 CP = 0
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paul@2 | 294 | 74HC273 #3 D[7...0] = D[7...0]
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paul@2 | 295 | WE# = 1
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paul@0 | 296 |
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paul@0 | 297 | Read Data
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paul@0 | 298 | ---------
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paul@0 | 299 |
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paul@0 | 300 | Configure pins as Q[7...0]
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paul@2 | 301 | OE# = 0
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paul@2 | 302 | 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
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paul@2 | 303 | Q[7...0] = 74HC273 #0 Q[7...0]
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paul@2 | 304 | OE# = 1
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paul@25 | 305 |
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paul@25 | 306 | Pins
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paul@25 | 307 | ====
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paul@25 | 308 |
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paul@25 | 309 | A0-A16 17-bit addressing
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paul@25 | 310 | DQ0-DQ7 8-bit data transfer
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paul@25 | 311 | CE# chip enable
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paul@25 | 312 | OE# output enable
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paul@25 | 313 | WE# write enable
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paul@25 | 314 | VCC 5V
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paul@25 | 315 | VSS ground
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paul@25 | 316 | NC (not connected)
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paul@25 | 317 |
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paul@25 | 318 | Low-Level Operations
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paul@25 | 319 | ====================
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paul@25 | 320 |
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paul@25 | 321 | CE# high standby
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paul@25 | 322 | CE# low read, write or output disable
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paul@25 | 323 |
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paul@25 | 324 | OE# high, WE# high output disable
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paul@25 | 325 | OE# low, WE# high read
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paul@25 | 326 | OE# high, WE# low write
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paul@25 | 327 |
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paul@25 | 328 | Thus, for reading and writing:
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paul@25 | 329 |
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paul@25 | 330 | OE# = not WE#
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paul@25 | 331 |
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paul@25 | 332 | Timing
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paul@25 | 333 | ======
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paul@25 | 334 |
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paul@25 | 335 | According to the datasheet, addresses are latched on the falling edge of the
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paul@25 | 336 | latest of WE# and CE#, data is latched on the rising edge of the latest of WE#
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paul@25 | 337 | and CE#.
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paul@25 | 338 |
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paul@25 | 339 | Strategy:
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paul@25 | 340 |
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paul@25 | 341 | 1. Start with CE#, OE#, WE# high (standby, output disable)
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paul@25 | 342 | 2. Bring CE# low (output disable)
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paul@25 | 343 | 3. Set addresses
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paul@25 | 344 | 4. Bring WE# or OE# low for operation (write or read)
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paul@25 | 345 | 5. Read or write data
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paul@25 | 346 | 6. Bring WE# or OE# high (output disable)
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paul@25 | 347 |
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paul@25 | 348 | Operation Modes
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paul@25 | 349 | ===============
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paul@25 | 350 |
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paul@25 | 351 | By default, the device is in read mode, meaning that merely bringing OE# low
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paul@25 | 352 | will produce data for the asserted address.
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paul@25 | 353 |
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paul@25 | 354 | To issue commands to change the mode involves write operations with specific
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paul@25 | 355 | address and data arguments.
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paul@25 | 356 |
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paul@25 | 357 | Sectors
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paul@25 | 358 | =======
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paul@25 | 359 |
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paul@25 | 360 | A[16...14] selects each 16KB sector and is referred to as the sector address
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paul@25 | 361 | or SA in the documentation.
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paul@25 | 362 |
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paul@25 | 363 | Commands
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paul@25 | 364 | ========
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paul@25 | 365 |
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paul@25 | 366 | Reset (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$F0)
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paul@25 | 367 |
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paul@25 | 368 | Autoselect (manufacturer) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
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paul@25 | 369 | (A=$X00; read)
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paul@25 | 370 | => D=$01
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paul@25 | 371 |
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paul@25 | 372 | Autoselect (device) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
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paul@25 | 373 | (A=$X01; read)
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paul@25 | 374 | => D=$20
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paul@25 | 375 |
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paul@25 | 376 | Simple reset (A=$XXXX; D=$F0)
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paul@25 | 377 |
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paul@25 | 378 | Sector erase (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$80);
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paul@25 | 379 | (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=SA; D=$30)
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paul@25 | 380 |
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paul@25 | 381 | Program (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$A0);
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paul@25 | 382 | (A=PA; D=PD)
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paul@25 | 383 |
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paul@25 | 384 | Progress
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paul@25 | 385 | --------
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paul@25 | 386 |
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paul@25 | 387 | Programming and erasure commands employ data pins as follows:
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paul@25 | 388 |
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paul@25 | 389 | Programming Erasure
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paul@25 | 390 | DQ7 On completion: DQ7-out On completion: 1
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paul@25 | 391 | DQ6 During: toggling value During: toggling value
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paul@25 | 392 | DQ5 On failure: 1 On failure: 1
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paul@25 | 393 | DQ3 Sector erase begun: 1
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paul@25 | 394 |
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paul@25 | 395 | A read operation is required to obtain these outputs, typically with the same
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paul@25 | 396 | address used to initiate each operation.
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