paul@6 | 1 | The Am29F010-90PC product has been used to test the software and hardware
|
paul@6 | 2 | design described here.
|
paul@6 | 3 |
|
paul@25 | 4 | Using the Software
|
paul@25 | 5 | ==================
|
paul@25 | 6 |
|
paul@25 | 7 | First of all, to use the Arduino-based programming solution, the Arduino needs
|
paul@25 | 8 | to have a program transferred to it. The program is compiled using the
|
paul@25 | 9 | Makefile provided, using the simple command...
|
paul@25 | 10 |
|
paul@25 | 11 | make
|
paul@25 | 12 |
|
paul@25 | 13 | To upload the program, the "upload" target is used as follows:
|
paul@25 | 14 |
|
paul@25 | 15 | make upload
|
paul@25 | 16 |
|
paul@25 | 17 | It is likely that this will fail unless appropriate permissions are available
|
paul@25 | 18 | on the device through which the Arduino is accessed on the host machine. Thus,
|
paul@25 | 19 | a privileged invocation is likely to be necessary:
|
paul@25 | 20 |
|
paul@25 | 21 | sudo make upload
|
paul@25 | 22 |
|
paul@25 | 23 | With the program uploaded, it should now be possible to communicate with the
|
paul@25 | 24 | Arduino. Unless the programming circuit has been constructed, however, there
|
paul@25 | 25 | will not be any effect of communicating with the Arduino, other than to check
|
paul@25 | 26 | that the program is operational. Running the upload.py script as follows will
|
paul@25 | 27 | permit such a test:
|
paul@25 | 28 |
|
paul@25 | 29 | ./upload.py -i
|
paul@25 | 30 |
|
paul@25 | 31 | Again, it is likely that this will need to be run in a privileged fashion as
|
paul@25 | 32 | follows:
|
paul@25 | 33 |
|
paul@25 | 34 | sudo ./upload.py -i
|
paul@25 | 35 |
|
paul@25 | 36 | The script should act as a terminal, showing a ">" prompt that can accept
|
paul@25 | 37 | various commands. Merely getting the prompt should be enough of an indication
|
paul@25 | 38 | that the program is functioning on the device.
|
paul@25 | 39 |
|
paul@25 | 40 | Once the programming circuit has been constructed (see "Arduino Interfacing"
|
paul@25 | 41 | below), the upload.py script can be used to upload data to the Am29F010
|
paul@25 | 42 | device. For example:
|
paul@25 | 43 |
|
paul@25 | 44 | sudo ./upload.py jungle.rom
|
paul@25 | 45 |
|
paul@25 | 46 | This will take jungle.rom and write it to the first sector of the Am29F010. To
|
paul@25 | 47 | verify the operation, the following command can be used:
|
paul@25 | 48 |
|
paul@25 | 49 | sudo ./upload.py -v jungle.rom
|
paul@25 | 50 |
|
paul@25 | 51 | To write to other sectors, an option can be specified. For example:
|
paul@25 | 52 |
|
paul@25 | 53 | sudo ./upload.py -s 1 junglecode.rom
|
paul@25 | 54 |
|
paul@25 | 55 | Again, the operation can be verified as follows:
|
paul@25 | 56 |
|
paul@25 | 57 | sudo ./upload.py -s 1 -v junglecode.rom
|
paul@25 | 58 |
|
paul@25 | 59 | Note that the -s option must appear first.
|
paul@25 | 60 |
|
paul@25 | 61 | The upload.py script can accept multiple files and will write each of them to
|
paul@25 | 62 | consecutive sectors. However, it can be more prudent to write files
|
paul@25 | 63 | individually, especially if the circuit is behaving in a less than completely
|
paul@25 | 64 | reliable fashion.
|
paul@25 | 65 |
|
paul@17 | 66 | Device Compatibility
|
paul@17 | 67 | ====================
|
paul@17 | 68 |
|
paul@17 | 69 | For use with an Acorn Electron ROM cartridge or other board providing a ROM
|
paul@17 | 70 | socket, the compatibility of the Am29F010 needs to be assessed in the context
|
paul@17 | 71 | of the ROM sockets likely to be provided.
|
paul@17 | 72 |
|
paul@17 | 73 | Original ROM Pinout Am29F010 Pinout
|
paul@17 | 74 | ------------------- ---------------
|
paul@17 | 75 |
|
paul@17 | 76 | 1 \/ 32 VCC
|
paul@17 | 77 | A16 2 31 WE#
|
paul@17 | 78 | 1 \/ 28 VCC A15 3 30
|
paul@17 | 79 | A12 2 27 A14 A12 4 29 A14
|
paul@17 | 80 | A7 3 26 A13 A7 5 28 A13
|
paul@17 | 81 | A6 4 25 A8 A6 6 27 A8
|
paul@17 | 82 | A5 5 24 A9 A5 7 26 A9
|
paul@17 | 83 | A4 6 23 A11 A4 8 25 A11
|
paul@17 | 84 | A3 7 22 OE# A3 9 24 OE#
|
paul@17 | 85 | A2 8 21 A10 A2 10 23 A10
|
paul@17 | 86 | A1 9 20 CS# A1 11 22 CE#
|
paul@17 | 87 | A0 10 19 D7 A0 12 21 DQ7
|
paul@17 | 88 | D0 11 18 D6 DQ0 13 20 DQ6
|
paul@17 | 89 | D1 12 17 D5 DQ1 14 19 DQ5
|
paul@17 | 90 | D2 13 16 D4 DQ2 15 18 DQ4
|
paul@17 | 91 | GND 14 15 D3 GND/VSS 16 17 DQ3
|
paul@17 | 92 |
|
paul@17 | 93 | Superimposing the Am29F010 onto a ROM socket would provide compatibility for
|
paul@17 | 94 | all pins from A12 to GND/VSS and from A14 to D3/DQ3.
|
paul@17 | 95 |
|
paul@17 | 96 | Pin 1 in a ROM socket would correspond to A15 but is not necessarily
|
paul@17 | 97 | connected, nor, perhaps, is A14 since only 14 bits are required to address 16
|
paul@17 | 98 | kilobytes, although there may be 32 kilobyte sockets connecting A14 and using
|
paul@20 | 99 | 15 bits to address 32K. A16 and A15 would probably be connected to ground to
|
paul@20 | 100 | ensure correct operation, but could also be wired to a selection mechanism so
|
paul@20 | 101 | that the entire contents of the flash memory might be exposed.
|
paul@17 | 102 |
|
paul@17 | 103 | Pin 28 is a ROM socket would provide power, but the corresponding pin 30 on an
|
paul@17 | 104 | Am29F010 is not connected. Thus pin 30 would need routing to pin 32 for the
|
paul@17 | 105 | flash device socket.
|
paul@17 | 106 |
|
paul@17 | 107 | Pin 31 for the Am29F010 would need to be asserted. Thus pin 30 might also be
|
paul@17 | 108 | routed to pin 31, so that the device would remain read-only at all times.
|
paul@17 | 109 |
|
paul@20 | 110 | Dual ROM Adapter Usage
|
paul@20 | 111 | ======================
|
paul@20 | 112 |
|
paul@20 | 113 | A single Am29F010 device could be wired to two ROM sockets in order to provide
|
paul@20 | 114 | data to both. The above wiring guide would be employed, with connections from
|
paul@20 | 115 | both sockets being connected to the Am29F010, but additional logic would be
|
paul@20 | 116 | required for the CS# signals originating from the sockets in order to expose
|
paul@20 | 117 | the appropriate region of flash memory. ROM #1 would be served by a "lower"
|
paul@20 | 118 | 16K region; ROM #2 would be served by an "upper" 16K region; A14 would be used
|
paul@20 | 119 | to switch between these regions.
|
paul@20 | 120 |
|
paul@20 | 121 | When ROM #1's CS# signal is low, an attempt to read from ROM #1 would be
|
paul@20 | 122 | occurring, and thus A14 would be held low. And when ROM #2's CS# signal is
|
paul@20 | 123 | low, an attempt to read from ROM #2 would be occurring, and thus A14 would be
|
paul@20 | 124 | held high.
|
paul@20 | 125 |
|
paul@22 | 126 | Meanwhile, the CS# signal for the two ROM sockets would need to be combined to
|
paul@22 | 127 | produce a resultant CE# signal for the Am29F010.
|
paul@22 | 128 |
|
paul@22 | 129 | ROM #1 CS# ROM #2 CS# Am29F010 A14 Am29F010 CE#
|
paul@22 | 130 | ---------- ---------- ------------ ------------
|
paul@22 | 131 | 0 0 Not defined Not defined
|
paul@22 | 132 | 0 1 0 0
|
paul@22 | 133 | 1 0 1 0
|
paul@22 | 134 | 1 1 Not defined 1
|
paul@20 | 135 |
|
paul@22 | 136 | It might therefore be possible to connect A14 to ROM #1's CS# signal. And the
|
paul@22 | 137 | resultant CE# signal could be the product of an AND gate:
|
paul@22 | 138 |
|
paul@22 | 139 | Am29F010 CE# = ROM #1 CS# AND ROM #2 CS#
|
paul@22 | 140 |
|
paul@25 | 141 | Wiring Details
|
paul@25 | 142 | --------------
|
paul@25 | 143 |
|
paul@22 | 144 | ROM #1 ROM #2 74HC08 Am29F010
|
paul@22 | 145 | ------ ------ ------ --------
|
paul@22 | 146 | CS# 1A A14
|
paul@22 | 147 | CS# 1B
|
paul@22 | 148 | 1Y CE#
|
paul@25 | 149 | OE# OE#
|
paul@0 | 150 |
|
paul@25 | 151 | ROM (Common) 74HC08 Am29F010
|
paul@25 | 152 | ------------ ------ --------
|
paul@25 | 153 | VCC VCC
|
paul@25 | 154 | GND GND
|
paul@25 | 155 | VCC VCC
|
paul@25 | 156 | VCC WE#
|
paul@25 | 157 | D0 DQ0
|
paul@25 | 158 | D1 DQ1
|
paul@25 | 159 | D2 DQ2
|
paul@25 | 160 | D3 DQ3
|
paul@25 | 161 | D4 DQ4
|
paul@25 | 162 | D5 DQ5
|
paul@25 | 163 | D6 DQ6
|
paul@25 | 164 | D7 DQ7
|
paul@25 | 165 | A0 A0
|
paul@25 | 166 | A1 A1
|
paul@25 | 167 | A2 A2
|
paul@25 | 168 | A3 A3
|
paul@25 | 169 | A4 A4
|
paul@25 | 170 | A5 A5
|
paul@25 | 171 | A6 A6
|
paul@25 | 172 | A7 A7
|
paul@25 | 173 | A8 A8
|
paul@25 | 174 | A9 A9
|
paul@25 | 175 | A10 A10
|
paul@25 | 176 | A11 A11
|
paul@25 | 177 | A12 A12
|
paul@25 | 178 | A13 A13
|
paul@25 | 179 | GND A15
|
paul@25 | 180 | GND A16
|
paul@25 | 181 | GND GND
|
paul@0 | 182 |
|
paul@0 | 183 | Arduino Interfacing
|
paul@0 | 184 | ===================
|
paul@0 | 185 |
|
paul@0 | 186 | Arduino can employ at most 14 digital pins, whereas the Am29F010B requires 17
|
paul@0 | 187 | address pins, 8 data pins, plus 3 control pins to be utilised.
|
paul@0 | 188 |
|
paul@0 | 189 | One solution is to map the 3 control pins directly to the Arduino, then to
|
paul@0 | 190 | channel address and data via 8 common pins to latches, and then employ the
|
paul@0 | 191 | remaining pins to control the latches.
|
paul@0 | 192 |
|
paul@2 | 193 | Two pins can be used to select the latches, and when neither latch is
|
paul@2 | 194 | selected, the data pins will be used to read or write data from the flash
|
paul@2 | 195 | memory.
|
paul@0 | 196 |
|
paul@0 | 197 | As a result, only 13 pins are needed on the Arduino.
|
paul@0 | 198 |
|
paul@21 | 199 | 74HC273 Pinout
|
paul@21 | 200 | --------------
|
paul@21 | 201 |
|
paul@21 | 202 | MR# 1 \/ 20 VCC
|
paul@21 | 203 | Q0 2 19 Q7
|
paul@21 | 204 | D0 3 18 D7
|
paul@21 | 205 | D1 4 17 D6
|
paul@21 | 206 | Q1 5 16 Q6
|
paul@21 | 207 | Q2 6 15 Q5
|
paul@21 | 208 | D2 7 14 D5
|
paul@21 | 209 | D3 8 13 D4
|
paul@21 | 210 | Q3 9 12 Q4
|
paul@21 | 211 | GND 10 11 CP
|
paul@21 | 212 |
|
paul@3 | 213 | Arduino 74HC273 #1 74HC273 #2 Am29F010
|
paul@3 | 214 | ------- ---------- ---------- --------
|
paul@5 | 215 | A5 CE#
|
paul@14 | 216 | A4 OE#
|
paul@14 | 217 | A3 WE#
|
paul@14 | 218 | 2 CP
|
paul@14 | 219 | 3 CP
|
paul@17 | 220 | 4 D0 D0 DQ0
|
paul@17 | 221 | 5 D1 D1 DQ1
|
paul@17 | 222 | 6 D2 D2 DQ2
|
paul@17 | 223 | 7 D3 D3 DQ3
|
paul@17 | 224 | 8 D4 D4 DQ4
|
paul@17 | 225 | 9 D5 D5 DQ5
|
paul@17 | 226 | 10 D6 D6 DQ6
|
paul@17 | 227 | 11 D7 D7 DQ7
|
paul@2 | 228 | Q0 A0
|
paul@2 | 229 | Q1 A1
|
paul@2 | 230 | Q2 A2
|
paul@2 | 231 | Q3 A3
|
paul@2 | 232 | Q4 A4
|
paul@2 | 233 | Q5 A5
|
paul@2 | 234 | Q6 A6
|
paul@2 | 235 | Q7 A7
|
paul@2 | 236 | Q0 A8
|
paul@2 | 237 | Q1 A9
|
paul@2 | 238 | Q2 A10
|
paul@2 | 239 | Q3 A11
|
paul@2 | 240 | Q4 A12
|
paul@2 | 241 | Q5 A13
|
paul@2 | 242 | Q6 A14
|
paul@2 | 243 | Q7 A15
|
paul@2 | 244 | GND A16 (not used)
|
paul@17 | 245 | 5V MR# MR#
|
paul@2 | 246 | 5V VCC VCC VCC
|
paul@2 | 247 | GND GND GND VSS
|
paul@0 | 248 |
|
paul@0 | 249 | Set Address
|
paul@0 | 250 | -----------
|
paul@0 | 251 |
|
paul@2 | 252 | 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
|
paul@2 | 253 | 74HC273 #1 D[7...0] = A[7...0]
|
paul@2 | 254 | 74HC273 #1 CP = 0; 74HC273 #2 CP = 1
|
paul@2 | 255 | 74HC273 #2 D[7...0] = A[15...8]
|
paul@0 | 256 |
|
paul@0 | 257 | Write Data
|
paul@0 | 258 | ----------
|
paul@0 | 259 |
|
paul@0 | 260 | Configure pins as D[7...0]
|
paul@2 | 261 | WE# = 0
|
paul@2 | 262 | 74HC273 #1 CP = 0; 74HC273 #2 CP = 0
|
paul@2 | 263 | 74HC273 #3 D[7...0] = D[7...0]
|
paul@2 | 264 | WE# = 1
|
paul@0 | 265 |
|
paul@0 | 266 | Read Data
|
paul@0 | 267 | ---------
|
paul@0 | 268 |
|
paul@0 | 269 | Configure pins as Q[7...0]
|
paul@2 | 270 | OE# = 0
|
paul@2 | 271 | 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
|
paul@2 | 272 | Q[7...0] = 74HC273 #0 Q[7...0]
|
paul@2 | 273 | OE# = 1
|
paul@25 | 274 |
|
paul@25 | 275 | Pins
|
paul@25 | 276 | ====
|
paul@25 | 277 |
|
paul@25 | 278 | A0-A16 17-bit addressing
|
paul@25 | 279 | DQ0-DQ7 8-bit data transfer
|
paul@25 | 280 | CE# chip enable
|
paul@25 | 281 | OE# output enable
|
paul@25 | 282 | WE# write enable
|
paul@25 | 283 | VCC 5V
|
paul@25 | 284 | VSS ground
|
paul@25 | 285 | NC (not connected)
|
paul@25 | 286 |
|
paul@25 | 287 | Low-Level Operations
|
paul@25 | 288 | ====================
|
paul@25 | 289 |
|
paul@25 | 290 | CE# high standby
|
paul@25 | 291 | CE# low read, write or output disable
|
paul@25 | 292 |
|
paul@25 | 293 | OE# high, WE# high output disable
|
paul@25 | 294 | OE# low, WE# high read
|
paul@25 | 295 | OE# high, WE# low write
|
paul@25 | 296 |
|
paul@25 | 297 | Thus, for reading and writing:
|
paul@25 | 298 |
|
paul@25 | 299 | OE# = not WE#
|
paul@25 | 300 |
|
paul@25 | 301 | Timing
|
paul@25 | 302 | ======
|
paul@25 | 303 |
|
paul@25 | 304 | According to the datasheet, addresses are latched on the falling edge of the
|
paul@25 | 305 | latest of WE# and CE#, data is latched on the rising edge of the latest of WE#
|
paul@25 | 306 | and CE#.
|
paul@25 | 307 |
|
paul@25 | 308 | Strategy:
|
paul@25 | 309 |
|
paul@25 | 310 | 1. Start with CE#, OE#, WE# high (standby, output disable)
|
paul@25 | 311 | 2. Bring CE# low (output disable)
|
paul@25 | 312 | 3. Set addresses
|
paul@25 | 313 | 4. Bring WE# or OE# low for operation (write or read)
|
paul@25 | 314 | 5. Read or write data
|
paul@25 | 315 | 6. Bring WE# or OE# high (output disable)
|
paul@25 | 316 |
|
paul@25 | 317 | Operation Modes
|
paul@25 | 318 | ===============
|
paul@25 | 319 |
|
paul@25 | 320 | By default, the device is in read mode, meaning that merely bringing OE# low
|
paul@25 | 321 | will produce data for the asserted address.
|
paul@25 | 322 |
|
paul@25 | 323 | To issue commands to change the mode involves write operations with specific
|
paul@25 | 324 | address and data arguments.
|
paul@25 | 325 |
|
paul@25 | 326 | Sectors
|
paul@25 | 327 | =======
|
paul@25 | 328 |
|
paul@25 | 329 | A[16...14] selects each 16KB sector and is referred to as the sector address
|
paul@25 | 330 | or SA in the documentation.
|
paul@25 | 331 |
|
paul@25 | 332 | Commands
|
paul@25 | 333 | ========
|
paul@25 | 334 |
|
paul@25 | 335 | Reset (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$F0)
|
paul@25 | 336 |
|
paul@25 | 337 | Autoselect (manufacturer) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
|
paul@25 | 338 | (A=$X00; read)
|
paul@25 | 339 | => D=$01
|
paul@25 | 340 |
|
paul@25 | 341 | Autoselect (device) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
|
paul@25 | 342 | (A=$X01; read)
|
paul@25 | 343 | => D=$20
|
paul@25 | 344 |
|
paul@25 | 345 | Simple reset (A=$XXXX; D=$F0)
|
paul@25 | 346 |
|
paul@25 | 347 | Sector erase (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$80);
|
paul@25 | 348 | (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=SA; D=$30)
|
paul@25 | 349 |
|
paul@25 | 350 | Program (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$A0);
|
paul@25 | 351 | (A=PA; D=PD)
|
paul@25 | 352 |
|
paul@25 | 353 | Progress
|
paul@25 | 354 | --------
|
paul@25 | 355 |
|
paul@25 | 356 | Programming and erasure commands employ data pins as follows:
|
paul@25 | 357 |
|
paul@25 | 358 | Programming Erasure
|
paul@25 | 359 | DQ7 On completion: DQ7-out On completion: 1
|
paul@25 | 360 | DQ6 During: toggling value During: toggling value
|
paul@25 | 361 | DQ5 On failure: 1 On failure: 1
|
paul@25 | 362 | DQ3 Sector erase begun: 1
|
paul@25 | 363 |
|
paul@25 | 364 | A read operation is required to obtain these outputs, typically with the same
|
paul@25 | 365 | address used to initiate each operation.
|