1 The Am29F010-90PC product has been used to test the software and hardware
2 design described here.
3
4 Device Compatibility
5 ====================
6
7 For use with an Acorn Electron ROM cartridge or other board providing a ROM
8 socket, the compatibility of the Am29F010 needs to be assessed in the context
9 of the ROM sockets likely to be provided.
10
11 Original ROM Pinout Am29F010 Pinout
12 ------------------- ---------------
13
14 1 \/ 32 VCC
15 A16 2 31 WE#
16 1 \/ 28 VCC A15 3 30
17 A12 2 27 A14 A12 4 29 A14
18 A7 3 26 A13 A7 5 28 A13
19 A6 4 25 A8 A6 6 27 A8
20 A5 5 24 A9 A5 7 26 A9
21 A4 6 23 A11 A4 8 25 A11
22 A3 7 22 OE# A3 9 24 OE#
23 A2 8 21 A10 A2 10 23 A10
24 A1 9 20 CS# A1 11 22 CE#
25 A0 10 19 D7 A0 12 21 DQ7
26 D0 11 18 D6 DQ0 13 20 DQ6
27 D1 12 17 D5 DQ1 14 19 DQ5
28 D2 13 16 D4 DQ2 15 18 DQ4
29 GND 14 15 D3 GND/VSS 16 17 DQ3
30
31 Superimposing the Am29F010 onto a ROM socket would provide compatibility for
32 all pins from A12 to GND/VSS and from A14 to D3/DQ3.
33
34 Pin 1 in a ROM socket would correspond to A15 but is not necessarily
35 connected, nor, perhaps, is A14 since only 14 bits are required to address 16
36 kilobytes, although there may be 32 kilobyte sockets connecting A14 and using
37 15 bits to address 32K. A16 and A15 would probably be connected to ground to
38 ensure correct operation, but could also be wired to a selection mechanism so
39 that the entire contents of the flash memory might be exposed.
40
41 Pin 28 is a ROM socket would provide power, but the corresponding pin 30 on an
42 Am29F010 is not connected. Thus pin 30 would need routing to pin 32 for the
43 flash device socket.
44
45 Pin 31 for the Am29F010 would need to be asserted. Thus pin 30 might also be
46 routed to pin 31, so that the device would remain read-only at all times.
47
48 Dual ROM Adapter Usage
49 ======================
50
51 A single Am29F010 device could be wired to two ROM sockets in order to provide
52 data to both. The above wiring guide would be employed, with connections from
53 both sockets being connected to the Am29F010, but additional logic would be
54 required for the CS# signals originating from the sockets in order to expose
55 the appropriate region of flash memory. ROM #1 would be served by a "lower"
56 16K region; ROM #2 would be served by an "upper" 16K region; A14 would be used
57 to switch between these regions.
58
59 When ROM #1's CS# signal is low, an attempt to read from ROM #1 would be
60 occurring, and thus A14 would be held low. And when ROM #2's CS# signal is
61 low, an attempt to read from ROM #2 would be occurring, and thus A14 would be
62 held high.
63
64 Meanwhile, the CS# signal for the two ROM sockets would need to be combined to
65 produce a resultant CE# signal for the Am29F010.
66
67 ROM #1 CS# ROM #2 CS# Am29F010 A14 Am29F010 CE#
68 ---------- ---------- ------------ ------------
69 0 0 Not defined Not defined
70 0 1 0 0
71 1 0 1 0
72 1 1 Not defined 1
73
74 It might therefore be possible to connect A14 to ROM #1's CS# signal. And the
75 resultant CE# signal could be the product of an AND gate:
76
77 Am29F010 CE# = ROM #1 CS# AND ROM #2 CS#
78
79 ROM #1 ROM #2 74HC08 Am29F010
80 ------ ------ ------ --------
81 CS# 1A A14
82 CS# 1B
83 1Y CE#
84
85 Pins
86 ====
87
88 A0-A16 17-bit addressing
89 DQ0-DQ7 8-bit data transfer
90 CE# chip enable
91 OE# output enable
92 WE# write enable
93 VCC 5V
94 VSS ground
95 NC (not connected)
96
97 Low-Level Operations
98 ====================
99
100 CE# high standby
101 CE# low read, write or output disable
102
103 OE# high, WE# high output disable
104 OE# low, WE# high read
105 OE# high, WE# low write
106
107 Thus, for reading and writing:
108
109 OE# = not WE#
110
111 Timing
112 ======
113
114 Addresses are latched on the falling edge of the latest of WE# and CE#
115 Data is latched on the rising edge of the latest of WE# and CE#
116
117 Strategy:
118
119 1. Start with CE#, OE#, WE# high (standby, output disable)
120 2. Bring CE# low (output disable)
121 3. Set addresses
122 4. Bring WE# or OE# low for operation (write or read)
123 5. Read or write data
124 6. Bring WE# or OE# high (output disable)
125
126 Operation Modes
127 ===============
128
129 By default, the device is in read mode, meaning that merely bringing OE# low
130 will produce data for the asserted address.
131
132 To issue commands to change the mode involves write operations with specific
133 address and data arguments.
134
135 Sectors
136 =======
137
138 A[16...14] selects each 16KB sector and is referred to as the sector address
139 or SA in the documentation.
140
141 Commands
142 ========
143
144 Reset (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$F0)
145
146 Autoselect (manufacturer) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
147 (A=$X00; read)
148 => D=$01
149
150 Autoselect (device) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
151 (A=$X01; read)
152 => D=$20
153
154 Simple reset (A=$XXXX; D=$F0)
155
156 Sector erase (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$80);
157 (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=SA; D=$30)
158
159 Program (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$A0);
160 (A=PA; D=PD)
161
162 Progress
163 --------
164
165 Programming and erasure commands employ data pins as follows:
166
167 Programming Erasure
168 DQ7 On completion: DQ7-out On completion: 1
169 DQ6 During: toggling value During: toggling value
170 DQ5 On failure: 1 On failure: 1
171 DQ3 Sector erase begun: 1
172
173 A read operation is required to obtain these outputs, typically with the same
174 address used to initiate each operation.
175
176 Arduino Interfacing
177 ===================
178
179 Arduino can employ at most 14 digital pins, whereas the Am29F010B requires 17
180 address pins, 8 data pins, plus 3 control pins to be utilised.
181
182 One solution is to map the 3 control pins directly to the Arduino, then to
183 channel address and data via 8 common pins to latches, and then employ the
184 remaining pins to control the latches.
185
186 Two pins can be used to select the latches, and when neither latch is
187 selected, the data pins will be used to read or write data from the flash
188 memory.
189
190 As a result, only 13 pins are needed on the Arduino.
191
192 74HC273 Pinout
193 --------------
194
195 MR# 1 \/ 20 VCC
196 Q0 2 19 Q7
197 D0 3 18 D7
198 D1 4 17 D6
199 Q1 5 16 Q6
200 Q2 6 15 Q5
201 D2 7 14 D5
202 D3 8 13 D4
203 Q3 9 12 Q4
204 GND 10 11 CP
205
206 Arduino 74HC273 #1 74HC273 #2 Am29F010
207 ------- ---------- ---------- --------
208 A5 CE#
209 A4 OE#
210 A3 WE#
211 2 CP
212 3 CP
213 4 D0 D0 DQ0
214 5 D1 D1 DQ1
215 6 D2 D2 DQ2
216 7 D3 D3 DQ3
217 8 D4 D4 DQ4
218 9 D5 D5 DQ5
219 10 D6 D6 DQ6
220 11 D7 D7 DQ7
221 Q0 A0
222 Q1 A1
223 Q2 A2
224 Q3 A3
225 Q4 A4
226 Q5 A5
227 Q6 A6
228 Q7 A7
229 Q0 A8
230 Q1 A9
231 Q2 A10
232 Q3 A11
233 Q4 A12
234 Q5 A13
235 Q6 A14
236 Q7 A15
237 GND A16 (not used)
238 5V MR# MR#
239 5V VCC VCC VCC
240 GND GND GND VSS
241
242 Set Address
243 -----------
244
245 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
246 74HC273 #1 D[7...0] = A[7...0]
247 74HC273 #1 CP = 0; 74HC273 #2 CP = 1
248 74HC273 #2 D[7...0] = A[15...8]
249
250 Write Data
251 ----------
252
253 Configure pins as D[7...0]
254 WE# = 0
255 74HC273 #1 CP = 0; 74HC273 #2 CP = 0
256 74HC273 #3 D[7...0] = D[7...0]
257 WE# = 1
258
259 Read Data
260 ---------
261
262 Configure pins as Q[7...0]
263 OE# = 0
264 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
265 Q[7...0] = 74HC273 #0 Q[7...0]
266 OE# = 1
