paul@0 | 1 | /* |
paul@0 | 2 | * Blink LEDs using a PIC32 microcontroller. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 5 | * |
paul@0 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@0 | 7 | * it under the terms of the GNU General Public License as published by |
paul@0 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@0 | 9 | * (at your option) any later version. |
paul@0 | 10 | * |
paul@0 | 11 | * This program is distributed in the hope that it will be useful, |
paul@0 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 14 | * GNU General Public License for more details. |
paul@0 | 15 | * |
paul@0 | 16 | * You should have received a copy of the GNU General Public License |
paul@0 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@0 | 18 | */ |
paul@0 | 19 | |
paul@0 | 20 | #include "mips.h" |
paul@0 | 21 | #include "pic32.h" |
paul@0 | 22 | |
paul@0 | 23 | /* Disable JTAG functionality on pins. */ |
paul@0 | 24 | |
paul@0 | 25 | .section .devcfg0, "a" |
paul@0 | 26 | .word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */ |
paul@0 | 27 | |
paul@0 | 28 | /* |
paul@0 | 29 | Set the oscillator to be the FRC oscillator with PLL, with peripheral clock |
paul@0 | 30 | divided by 2, and FRCDIV+PLL selected. |
paul@0 | 31 | |
paul@0 | 32 | The watchdog timer (FWDTEN) is also disabled. |
paul@0 | 33 | |
paul@0 | 34 | The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with |
paul@0 | 35 | RPB4. |
paul@0 | 36 | */ |
paul@0 | 37 | |
paul@0 | 38 | .section .devcfg1, "a" |
paul@0 | 39 | .word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1; |
paul@0 | 40 | DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */ |
paul@0 | 41 | |
paul@0 | 42 | /* |
paul@0 | 43 | Set the FRC oscillator PLL function with an input division of 4, an output |
paul@0 | 44 | division of 2, a multiplication of 24, yielding a multiplication of 3. |
paul@0 | 45 | |
paul@0 | 46 | The FRC is apparently at 16MHz and this produces a system clock of 48MHz. |
paul@0 | 47 | */ |
paul@0 | 48 | |
paul@0 | 49 | .section .devcfg2, "a" |
paul@0 | 50 | .word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001; |
paul@0 | 51 | DEVCFG2<6:4> = FPLLMUL<2:0> = 111; |
paul@0 | 52 | DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */ |
paul@0 | 53 | |
paul@0 | 54 | .text |
paul@0 | 55 | .globl _start |
paul@0 | 56 | |
paul@0 | 57 | _start: |
paul@0 | 58 | /* Set pins for output. */ |
paul@0 | 59 | |
paul@0 | 60 | jal init_pins |
paul@0 | 61 | nop |
paul@0 | 62 | |
paul@0 | 63 | /* Clear output (LED). */ |
paul@0 | 64 | |
paul@0 | 65 | la $t0, PORTA |
paul@0 | 66 | li $t1, (1 << 3) /* PORTA<3> = RA3 */ |
paul@0 | 67 | sw $t1, CLR($t0) |
paul@0 | 68 | |
paul@0 | 69 | /* Main program. */ |
paul@0 | 70 | main: |
paul@0 | 71 | li $a1, (3 << 24) /* counter ~= 50000000 */ |
paul@0 | 72 | |
paul@0 | 73 | /* Monitoring loop. */ |
paul@0 | 74 | loop: |
paul@0 | 75 | addiu $a1, $a1, -1 /* counter -= 1 */ |
paul@0 | 76 | bnez $a1, loop |
paul@0 | 77 | nop |
paul@0 | 78 | |
paul@0 | 79 | /* Invert output (LED). */ |
paul@0 | 80 | |
paul@0 | 81 | la $t0, PORTA |
paul@0 | 82 | li $t1, (1 << 3) /* PORTA<3> = RA3 */ |
paul@0 | 83 | sw $t1, INV($t0) |
paul@0 | 84 | |
paul@0 | 85 | j main |
paul@0 | 86 | nop |
paul@0 | 87 | |
paul@0 | 88 | |
paul@0 | 89 | |
paul@0 | 90 | init_pins: |
paul@0 | 91 | /* DEVCFG0<2> needs setting to 0 before the program is run. */ |
paul@0 | 92 | |
paul@0 | 93 | la $v0, CFGCON |
paul@0 | 94 | li $v1, (1 << 3) /* CFGCON<3> = JTAGEN = 0 */ |
paul@0 | 95 | sw $v1, CLR($v0) |
paul@0 | 96 | |
paul@0 | 97 | init_outputs: |
paul@0 | 98 | /* Remove analogue features from pins. */ |
paul@0 | 99 | |
paul@0 | 100 | la $v0, ANSELA |
paul@0 | 101 | sw $zero, 0($v0) /* ANSELA = 0 */ |
paul@0 | 102 | la $v0, ANSELB |
paul@0 | 103 | sw $zero, 0($v0) /* ANSELB = 0 */ |
paul@0 | 104 | |
paul@0 | 105 | la $v0, TRISA |
paul@0 | 106 | sw $zero, 0($v0) |
paul@0 | 107 | la $v0, TRISB |
paul@0 | 108 | sw $zero, 0($v0) |
paul@0 | 109 | |
paul@0 | 110 | la $v0, PORTA |
paul@0 | 111 | sw $zero, 0($v0) |
paul@0 | 112 | la $v0, PORTB |
paul@0 | 113 | sw $zero, 0($v0) |
paul@0 | 114 | |
paul@0 | 115 | jr $ra |
paul@0 | 116 | nop |