paul@0 | 1 | #ifndef __PIC32_H__ |
paul@0 | 2 | #define __PIC32_H__ |
paul@0 | 3 | |
paul@0 | 4 | /* See... |
paul@0 | 5 | * TABLE 4-1: SFR MEMORYMAP |
paul@0 | 6 | * TABLE 11-3: PORTA REGISTER MAP |
paul@0 | 7 | * 11.2 CLR, SET and INV Registers |
paul@0 | 8 | * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet |
paul@0 | 9 | */ |
paul@0 | 10 | |
paul@0 | 11 | #define OC1CON 0xBF803000 |
paul@0 | 12 | #define OC1R 0xBF803010 |
paul@0 | 13 | #define OC1RS 0xBF803020 |
paul@0 | 14 | #define OC2CON 0xBF803200 |
paul@0 | 15 | #define OC2R 0xBF803210 |
paul@0 | 16 | #define OC2RS 0xBF803220 |
paul@0 | 17 | #define OC3CON 0xBF803400 |
paul@0 | 18 | #define OC3R 0xBF803410 |
paul@0 | 19 | #define OC3RS 0xBF803420 |
paul@0 | 20 | |
paul@0 | 21 | #define T1CON 0xBF800600 |
paul@0 | 22 | #define TMR1 0xBF800610 |
paul@0 | 23 | #define PR1 0xBF800620 |
paul@0 | 24 | #define T2CON 0xBF800800 |
paul@0 | 25 | #define TMR2 0xBF800810 |
paul@0 | 26 | #define PR2 0xBF800820 |
paul@0 | 27 | #define T3CON 0xBF800A00 |
paul@0 | 28 | #define TMR3 0xBF800A10 |
paul@0 | 29 | #define PR3 0xBF800A20 |
paul@0 | 30 | |
paul@0 | 31 | #define U1MODE 0xBF806000 |
paul@0 | 32 | #define U1STA 0xBF806010 |
paul@0 | 33 | #define U1TXREG 0xBF806020 |
paul@0 | 34 | #define U1RXREG 0xBF806030 |
paul@0 | 35 | #define U1BRG 0xBF806040 |
paul@0 | 36 | |
paul@0 | 37 | #define PMCON 0xBF807000 |
paul@0 | 38 | #define PMMODE 0xBF807010 |
paul@0 | 39 | #define PMADDR 0xBF807020 |
paul@0 | 40 | #define PMDOUT 0xBF807030 |
paul@0 | 41 | #define PMDIN 0xBF807040 |
paul@0 | 42 | #define PMAEN 0xBF807050 |
paul@0 | 43 | #define PMSTAT 0xBF807060 |
paul@0 | 44 | |
paul@0 | 45 | #define OSCCON 0xBF80F000 |
paul@0 | 46 | #define REFOCON 0xBF80F020 |
paul@0 | 47 | #define REFOTRIM 0xBF80F030 |
paul@0 | 48 | #define CFGCON 0xBF80F200 |
paul@0 | 49 | #define SYSKEY 0xBF80F230 |
paul@0 | 50 | |
paul@0 | 51 | #define U1RXR 0xBF80FA50 |
paul@0 | 52 | |
paul@0 | 53 | #define RPA0R 0xBF80FB00 |
paul@0 | 54 | #define RPA1R 0xBF80FB04 |
paul@0 | 55 | #define RPA2R 0xBF80FB08 |
paul@0 | 56 | #define RPA3R 0xBF80FB0C |
paul@0 | 57 | #define RPA4R 0xBF80FB10 |
paul@0 | 58 | #define RPB0R 0xBF80FB2C |
paul@0 | 59 | #define RPB1R 0xBF80FB30 |
paul@0 | 60 | #define RPB2R 0xBF80FB34 |
paul@0 | 61 | #define RPB3R 0xBF80FB38 |
paul@0 | 62 | #define RPB4R 0xBF80FB3C |
paul@0 | 63 | #define RPB5R 0xBF80FB40 |
paul@0 | 64 | #define RPB10R 0xBF80FB54 |
paul@0 | 65 | #define RPB15R 0xBF80FB68 |
paul@0 | 66 | |
paul@0 | 67 | #define INTCON 0xBF881000 |
paul@0 | 68 | #define IFS0 0xBF881030 |
paul@0 | 69 | #define IFS1 0xBF881040 |
paul@0 | 70 | #define IEC0 0xBF881060 |
paul@0 | 71 | #define IEC1 0xBF881070 |
paul@0 | 72 | #define IPC1 0xBF8810A0 |
paul@0 | 73 | #define IPC2 0xBF8810B0 |
paul@0 | 74 | #define IPC7 0xBF881100 |
paul@0 | 75 | #define IPC8 0xBF881110 |
paul@0 | 76 | #define IPC10 0xBF881130 |
paul@0 | 77 | |
paul@0 | 78 | #define BMXCON 0xBF882000 |
paul@0 | 79 | #define BMXDKPBA 0xBF882010 |
paul@0 | 80 | #define BMXDUDBA 0xBF882020 |
paul@0 | 81 | #define BMXDUPBA 0xBF882030 |
paul@0 | 82 | #define BMXDRMSZ 0xBF882040 |
paul@0 | 83 | |
paul@0 | 84 | #define DMACON 0xBF883000 |
paul@0 | 85 | #define DCH0CON 0xBF883060 |
paul@0 | 86 | #define DCH0ECON 0xBF883070 |
paul@0 | 87 | #define DCH0INT 0xBF883080 |
paul@0 | 88 | #define DCH0SSA 0xBF883090 |
paul@0 | 89 | #define DCH0DSA 0xBF8830A0 |
paul@0 | 90 | #define DCH0SSIZ 0xBF8830B0 |
paul@0 | 91 | #define DCH0DSIZ 0xBF8830C0 |
paul@0 | 92 | #define DCH0CSIZ 0xBF8830F0 |
paul@0 | 93 | #define DCH1CON 0xBF883120 |
paul@0 | 94 | #define DCH1ECON 0xBF883130 |
paul@0 | 95 | #define DCH1INT 0xBF883140 |
paul@0 | 96 | #define DCH1SSA 0xBF883150 |
paul@0 | 97 | #define DCH1DSA 0xBF883160 |
paul@0 | 98 | #define DCH1SSIZ 0xBF883170 |
paul@0 | 99 | #define DCH1DSIZ 0xBF883180 |
paul@0 | 100 | #define DCH1CSIZ 0xBF8831B0 |
paul@0 | 101 | #define DCH2CON 0xBF8831E0 |
paul@0 | 102 | #define DCH2ECON 0xBF8831F0 |
paul@0 | 103 | #define DCH2INT 0xBF883200 |
paul@0 | 104 | #define DCH2SSA 0xBF883210 |
paul@0 | 105 | #define DCH2DSA 0xBF883220 |
paul@0 | 106 | #define DCH2SSIZ 0xBF883230 |
paul@0 | 107 | #define DCH2DSIZ 0xBF883240 |
paul@0 | 108 | #define DCH2CSIZ 0xBF883270 |
paul@0 | 109 | |
paul@0 | 110 | #define ANSELA 0xBF886000 |
paul@0 | 111 | #define TRISA 0xBF886010 |
paul@0 | 112 | #define PORTA 0xBF886020 |
paul@0 | 113 | #define LATA 0xBF886030 |
paul@0 | 114 | #define ODCA 0xBF886040 |
paul@0 | 115 | #define ANSELB 0xBF886100 |
paul@0 | 116 | #define TRISB 0xBF886110 |
paul@0 | 117 | #define PORTB 0xBF886120 |
paul@0 | 118 | #define LATB 0xBF886130 |
paul@0 | 119 | #define ODCB 0xBF886140 |
paul@0 | 120 | |
paul@0 | 121 | #define CLR 0x4 |
paul@0 | 122 | #define SET 0x8 |
paul@0 | 123 | #define INV 0xC |
paul@0 | 124 | |
paul@0 | 125 | #endif /* __PIC32_H__ */ |