# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1539809415 -7200
# Node ID 7ca24825ce7ef8e1ecd3a9fed70ab6ae53a6b320
# Parent  47e3885a4c3ad8bb7df1d9966f074342131c1cda
Added various comments.

diff -r 47e3885a4c3a -r 7ca24825ce7e blink.S
--- a/blink.S	Mon Oct 15 21:59:18 2018 +0200
+++ b/blink.S	Wed Oct 17 22:50:15 2018 +0200
@@ -44,6 +44,9 @@
 division of 2, a multiplication of 24, yielding a multiplication of 3.
 
 The FRC is apparently at 16MHz and this produces a system clock of 48MHz.
+
+The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1
+settings.
 */
 
 .section .devcfg2, "a"
@@ -102,11 +105,15 @@
 	la $v0, ANSELB
 	sw $zero, 0($v0)	/* ANSELB = 0 */
 
+	/* Set pins as outputs. */
+
 	la $v0, TRISA
 	sw $zero, 0($v0)
 	la $v0, TRISB
 	sw $zero, 0($v0)
 
+	/* Clear outputs. */
+
 	la $v0, PORTA
 	sw $zero, 0($v0)
 	la $v0, PORTB