paul@15 | 1 | /* |
paul@15 | 2 | * A demonstration of various PIC32 peripherals. |
paul@15 | 3 | * |
paul@16 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@15 | 5 | * |
paul@15 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@15 | 7 | * it under the terms of the GNU General Public License as published by |
paul@15 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@15 | 9 | * (at your option) any later version. |
paul@15 | 10 | * |
paul@15 | 11 | * This program is distributed in the hope that it will be useful, |
paul@15 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@15 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@15 | 14 | * GNU General Public License for more details. |
paul@15 | 15 | * |
paul@15 | 16 | * You should have received a copy of the GNU General Public License |
paul@15 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@15 | 18 | */ |
paul@15 | 19 | |
paul@15 | 20 | |
paul@108 | 21 | #include "debug.h" |
paul@0 | 22 | #include "init.h" |
paul@108 | 23 | #include "pic32_c.h" |
paul@108 | 24 | #include "utils.h" |
paul@47 | 25 | |
paul@47 | 26 | /* Specific functionality. */ |
paul@47 | 27 | |
paul@16 | 28 | #include "main.h" |
paul@47 | 29 | #include "devconfig.h" |
paul@0 | 30 | |
paul@13 | 31 | static const char message1[] = "Hello!\r\n"; |
paul@44 | 32 | |
paul@44 | 33 | #define CELLSIZE4 |
paul@44 | 34 | |
paul@44 | 35 | #ifdef CELLSIZE1 |
paul@44 | 36 | static const char message2[] = "Adoc gi,hlo\r"; |
paul@44 | 37 | static const char message3[] = "n neaan el!\n"; |
paul@44 | 38 | #define CELLSIZE 1 |
paul@44 | 39 | #endif |
paul@44 | 40 | |
paul@44 | 41 | #ifdef CELLSIZE4 |
paul@44 | 42 | static const char message2[] = "And agahell"; |
paul@44 | 43 | static const char message3[] = "oncein, o!\r\n"; |
paul@44 | 44 | #define CELLSIZE 4 |
paul@44 | 45 | #endif |
paul@44 | 46 | |
paul@60 | 47 | static int uart_echo = 1; |
paul@0 | 48 | |
paul@15 | 49 | |
paul@15 | 50 | |
paul@16 | 51 | /* Main program. */ |
paul@16 | 52 | |
paul@0 | 53 | void main(void) |
paul@0 | 54 | { |
paul@0 | 55 | init_memory(); |
paul@0 | 56 | init_pins(); |
paul@0 | 57 | init_outputs(); |
paul@0 | 58 | |
paul@0 | 59 | unlock_config(); |
paul@0 | 60 | config_uart(); |
paul@0 | 61 | lock_config(); |
paul@0 | 62 | |
paul@11 | 63 | init_dma(); |
paul@3 | 64 | |
paul@26 | 65 | /* Peripheral relationships: |
paul@26 | 66 | |
paul@44 | 67 | Timer3 -> OC1 -> DMA0: message2 -> U1TXREG |
paul@44 | 68 | ___/ |
paul@44 | 69 | / |
paul@44 | 70 | Timer2 -> DMA1: message1 -> U1TXREG |
paul@26 | 71 | \___ |
paul@26 | 72 | \ |
paul@44 | 73 | Timer3 -> OC1 -> DMA2: message3 -> U1TXREG |
paul@26 | 74 | */ |
paul@26 | 75 | |
paul@44 | 76 | /* Enable DMA on the next channel's completion, with OC1 initiating |
paul@44 | 77 | transfers, raising a transfer completion interrupt to be handled. */ |
paul@44 | 78 | |
paul@44 | 79 | dma_init(0, 2); |
paul@44 | 80 | dma_set_chaining(0, dma_chain_next); |
paul@44 | 81 | dma_set_interrupt(0, OC1, 1); |
paul@44 | 82 | dma_set_transfer(0, PHYSICAL((uint32_t) message2), sizeof(message2) - 1, |
paul@44 | 83 | HW_PHYSICAL(UART_REG(1, UxTXREG)), 1, |
paul@44 | 84 | CELLSIZE); |
paul@44 | 85 | |
paul@13 | 86 | /* Initiate DMA on the Timer2 interrupt. Since the channel is not |
paul@20 | 87 | auto-enabled, it must be explicitly enabled elsewhere (when a UART |
paul@20 | 88 | interrupt is handled). */ |
paul@11 | 89 | |
paul@44 | 90 | dma_init(1, 3); |
paul@44 | 91 | dma_set_interrupt(1, T2, 1); |
paul@44 | 92 | dma_set_transfer(1, PHYSICAL((uint32_t) message1), sizeof(message1) - 1, |
paul@13 | 93 | HW_PHYSICAL(UART_REG(1, UxTXREG)), 1, |
paul@13 | 94 | 1); |
paul@13 | 95 | |
paul@14 | 96 | /* Enable DMA on the preceding channel's completion, with OC1 initiating |
paul@14 | 97 | transfers, raising a transfer completion interrupt to be handled. */ |
paul@13 | 98 | |
paul@44 | 99 | dma_init(2, 2); |
paul@44 | 100 | dma_set_chaining(2, dma_chain_previous); |
paul@44 | 101 | dma_set_interrupt(2, OC1, 1); |
paul@44 | 102 | dma_set_transfer(2, PHYSICAL((uint32_t) message3), sizeof(message3) - 1, |
paul@3 | 103 | HW_PHYSICAL(UART_REG(1, UxTXREG)), 1, |
paul@44 | 104 | CELLSIZE); |
paul@44 | 105 | dma_init_interrupt(2, 0b00001000, 7, 3); |
paul@13 | 106 | |
paul@14 | 107 | /* Configure a timer for the first DMA channel whose interrupt condition |
paul@26 | 108 | drives the transfer. The interrupt itself does not need to be enabled. */ |
paul@3 | 109 | |
paul@13 | 110 | timer_init(2, 0b111, 60000); |
paul@13 | 111 | timer_on(2); |
paul@13 | 112 | |
paul@14 | 113 | /* Configure a timer for the output compare unit below. */ |
paul@14 | 114 | |
paul@14 | 115 | timer_init(3, 0b111, 20000); |
paul@13 | 116 | timer_on(3); |
paul@13 | 117 | |
paul@14 | 118 | /* Configure output compare in dual compare (continuous output) mode using |
paul@14 | 119 | Timer3 as time base. The interrupt condition drives the second DMA |
paul@26 | 120 | channel but does not need to be enabled. */ |
paul@14 | 121 | |
paul@14 | 122 | oc_init(1, 0b101, 3); |
paul@14 | 123 | oc_set_pulse(1, 10000); |
paul@14 | 124 | oc_set_pulse_end(1, 20000); |
paul@14 | 125 | oc_on(1); |
paul@14 | 126 | |
paul@20 | 127 | /* Set UART interrupt priority above CPU priority to process events and to |
paul@20 | 128 | enable the first DMA channel. */ |
paul@3 | 129 | |
paul@47 | 130 | uart_init(1, FPB, 115200); |
paul@13 | 131 | uart_init_interrupt(1, UxRIF, 7, 3); |
paul@3 | 132 | uart_on(1); |
paul@0 | 133 | |
paul@0 | 134 | interrupts_on(); |
paul@0 | 135 | |
paul@0 | 136 | blink(3 << 24, PORTA, 1 << 3); |
paul@0 | 137 | } |
paul@0 | 138 | |
paul@16 | 139 | |
paul@16 | 140 | |
paul@16 | 141 | /* Exception and interrupt handlers. */ |
paul@16 | 142 | |
paul@0 | 143 | void exception_handler(void) |
paul@0 | 144 | { |
paul@79 | 145 | blink(1 << 22, PORTA, 1 << 3); |
paul@0 | 146 | } |
paul@0 | 147 | |
paul@0 | 148 | void interrupt_handler(void) |
paul@0 | 149 | { |
paul@19 | 150 | uint32_t ifs; |
paul@19 | 151 | char val; |
paul@11 | 152 | |
paul@3 | 153 | /* Check for a UART receive interrupt condition (UxRIF). */ |
paul@0 | 154 | |
paul@11 | 155 | ifs = REG(UARTIFS) & UART_INT_FLAGS(1, UxRIF); |
paul@8 | 156 | |
paul@8 | 157 | if (ifs) |
paul@3 | 158 | { |
paul@8 | 159 | /* Clear the UART interrupt condition. */ |
paul@8 | 160 | |
paul@8 | 161 | CLR_REG(UARTIFS, ifs); |
paul@8 | 162 | |
paul@3 | 163 | /* Write the received data back. */ |
paul@0 | 164 | |
paul@19 | 165 | while (uart_can_read(1)) |
paul@11 | 166 | { |
paul@19 | 167 | val = uart_read_char(1); |
paul@11 | 168 | if (uart_echo) |
paul@19 | 169 | uart_write_char(1, val); |
paul@13 | 170 | |
paul@13 | 171 | /* Initiate transfer upon receiving a particular character. */ |
paul@13 | 172 | |
paul@13 | 173 | if (val == '0') |
paul@44 | 174 | dma_on(1); |
paul@11 | 175 | } |
paul@11 | 176 | } |
paul@18 | 177 | |
paul@18 | 178 | /* Check for a DMA interrupt condition (CHBCIF). */ |
paul@18 | 179 | |
paul@44 | 180 | ifs = REG(DMAIFS) & DMA_INT_FLAGS(2, DCHxIF); |
paul@18 | 181 | |
paul@18 | 182 | if (ifs) |
paul@18 | 183 | { |
paul@18 | 184 | uart_write_string("CHBCIF\r\n"); |
paul@18 | 185 | INV_REG(PORTA, 1 << 2); |
paul@44 | 186 | CLR_REG(DMA_REG(2, DCHxINT), 0b11111111); |
paul@18 | 187 | CLR_REG(DMAIFS, ifs); |
paul@18 | 188 | } |
paul@0 | 189 | } |
paul@16 | 190 | |
paul@16 | 191 | |
paul@16 | 192 | |
paul@16 | 193 | /* Peripheral pin configuration. */ |
paul@16 | 194 | |
paul@16 | 195 | void config_uart(void) |
paul@16 | 196 | { |
paul@16 | 197 | /* Map U1RX to RPB13. */ |
paul@16 | 198 | |
paul@16 | 199 | REG(U1RXR) = 0b0011; /* U1RXR<3:0> = 0011 (RPB13) */ |
paul@16 | 200 | |
paul@16 | 201 | /* Map U1TX to RPB15. */ |
paul@16 | 202 | |
paul@16 | 203 | REG(RPB15R) = 0b0001; /* RPB15R<3:0> = 0001 (U1TX) */ |
paul@16 | 204 | |
paul@16 | 205 | /* Set RPB13 to input. */ |
paul@16 | 206 | |
paul@16 | 207 | SET_REG(TRISB, 1 << 13); |
paul@16 | 208 | } |