paul@0 | 1 | #include "pic32_c.h" |
paul@0 | 2 | #include "init.h" |
paul@11 | 3 | #include "debug.h" |
paul@0 | 4 | |
paul@13 | 5 | static const char message1[] = "Hello!\r\n"; |
paul@13 | 6 | static const char message2[] = "Again!\r\n"; |
paul@11 | 7 | static int uart_echo = 0; |
paul@0 | 8 | |
paul@0 | 9 | static void blink(uint32_t delay, uint32_t port, uint32_t pins) |
paul@0 | 10 | { |
paul@0 | 11 | uint32_t counter; |
paul@0 | 12 | |
paul@0 | 13 | /* Clear outputs (LED). */ |
paul@0 | 14 | |
paul@0 | 15 | CLR_REG(port, pins); |
paul@0 | 16 | |
paul@0 | 17 | while (1) |
paul@0 | 18 | { |
paul@0 | 19 | counter = delay; |
paul@0 | 20 | |
paul@0 | 21 | while (counter--) __asm__(""); /* retain loop */ |
paul@0 | 22 | |
paul@0 | 23 | /* Invert outputs (LED). */ |
paul@0 | 24 | |
paul@0 | 25 | INV_REG(port, pins); |
paul@0 | 26 | } |
paul@0 | 27 | } |
paul@0 | 28 | |
paul@0 | 29 | void main(void) |
paul@0 | 30 | { |
paul@0 | 31 | init_memory(); |
paul@0 | 32 | init_pins(); |
paul@0 | 33 | init_outputs(); |
paul@0 | 34 | |
paul@0 | 35 | unlock_config(); |
paul@0 | 36 | config_uart(); |
paul@0 | 37 | lock_config(); |
paul@0 | 38 | |
paul@11 | 39 | init_dma(); |
paul@3 | 40 | |
paul@13 | 41 | /* Initiate DMA on the Timer2 interrupt. Since the channel is not |
paul@13 | 42 | auto-enabled, it must be explicitly enabled upon completion. */ |
paul@11 | 43 | |
paul@11 | 44 | dma_init(0, 3); |
paul@13 | 45 | dma_set_interrupt(0, T2, 1); |
paul@13 | 46 | dma_set_transfer(0, PHYSICAL((uint32_t) message1), sizeof(message1) - 1, |
paul@13 | 47 | HW_PHYSICAL(UART_REG(1, UxTXREG)), 1, |
paul@13 | 48 | 1); |
paul@13 | 49 | |
paul@13 | 50 | /* Enable DMA on the preceding channel's completion, with Timer3 initiating |
paul@13 | 51 | transfers, raising a transfer completion interrupt. */ |
paul@13 | 52 | |
paul@13 | 53 | dma_init(1, 3); |
paul@13 | 54 | dma_set_chaining(1, dma_chain_previous); |
paul@13 | 55 | dma_set_interrupt(1, T3, 1); |
paul@13 | 56 | dma_set_transfer(1, PHYSICAL((uint32_t) message2), sizeof(message2) - 1, |
paul@3 | 57 | HW_PHYSICAL(UART_REG(1, UxTXREG)), 1, |
paul@3 | 58 | 1); |
paul@13 | 59 | dma_init_interrupt(1, 0b00001000, 7, 3); |
paul@13 | 60 | |
paul@13 | 61 | /* Configure timers. */ |
paul@3 | 62 | |
paul@13 | 63 | timer_init(2, 0b111, 60000); |
paul@13 | 64 | timer_init_interrupt(2, 1, 3); |
paul@13 | 65 | timer_on(2); |
paul@13 | 66 | |
paul@13 | 67 | timer_init(3, 0b111, 40000); |
paul@13 | 68 | timer_init_interrupt(3, 1, 3); |
paul@13 | 69 | timer_on(3); |
paul@13 | 70 | |
paul@13 | 71 | /* Set UART interrupt priority above CPU priority to process events. */ |
paul@3 | 72 | |
paul@3 | 73 | uart_init(1, 115200); |
paul@13 | 74 | uart_init_interrupt(1, UxRIF, 7, 3); |
paul@3 | 75 | uart_on(1); |
paul@0 | 76 | |
paul@0 | 77 | interrupts_on(); |
paul@0 | 78 | |
paul@0 | 79 | blink(3 << 24, PORTA, 1 << 3); |
paul@0 | 80 | } |
paul@0 | 81 | |
paul@0 | 82 | void exception_handler(void) |
paul@0 | 83 | { |
paul@0 | 84 | blink(3 << 12, PORTA, 1 << 3); |
paul@0 | 85 | } |
paul@0 | 86 | |
paul@0 | 87 | void interrupt_handler(void) |
paul@0 | 88 | { |
paul@11 | 89 | uint32_t ifs, val; |
paul@11 | 90 | |
paul@3 | 91 | /* Check for a UART receive interrupt condition (UxRIF). */ |
paul@0 | 92 | |
paul@11 | 93 | ifs = REG(UARTIFS) & UART_INT_FLAGS(1, UxRIF); |
paul@8 | 94 | |
paul@8 | 95 | if (ifs) |
paul@3 | 96 | { |
paul@8 | 97 | /* Clear the UART interrupt condition. */ |
paul@8 | 98 | |
paul@8 | 99 | CLR_REG(UARTIFS, ifs); |
paul@8 | 100 | |
paul@3 | 101 | /* Write the received data back. */ |
paul@0 | 102 | |
paul@3 | 103 | while (REG(UART_REG(1, UxSTA)) & 1) |
paul@11 | 104 | { |
paul@11 | 105 | val = REG(UART_REG(1, UxRXREG)); |
paul@11 | 106 | if (uart_echo) |
paul@11 | 107 | uart_write((char) val); |
paul@13 | 108 | |
paul@13 | 109 | /* Initiate transfer upon receiving a particular character. */ |
paul@13 | 110 | |
paul@13 | 111 | if (val == '0') |
paul@13 | 112 | dma_on(0); |
paul@11 | 113 | } |
paul@11 | 114 | } |
paul@11 | 115 | |
paul@11 | 116 | /* Check for a DMA interrupt condition (CHBCIF). */ |
paul@0 | 117 | |
paul@13 | 118 | ifs = REG(DMAIFS) & DMA_INT_FLAGS(1, 1); |
paul@11 | 119 | |
paul@11 | 120 | if (ifs) |
paul@11 | 121 | { |
paul@3 | 122 | INV_REG(PORTA, 1 << 2); |
paul@11 | 123 | CLR_REG(DMA_REG(0, DCHxINT), 0b11111111); |
paul@11 | 124 | CLR_REG(DMAIFS, ifs); |
paul@11 | 125 | |
paul@11 | 126 | dma_on(0); |
paul@3 | 127 | } |
paul@0 | 128 | } |