paul@37 | 1 | /* |
paul@37 | 2 | * Generate a VGA signal using a PIC32 microcontroller. |
paul@37 | 3 | * |
paul@37 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@37 | 5 | * |
paul@37 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@37 | 7 | * it under the terms of the GNU General Public License as published by |
paul@37 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@37 | 9 | * (at your option) any later version. |
paul@37 | 10 | * |
paul@37 | 11 | * This program is distributed in the hope that it will be useful, |
paul@37 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@37 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@37 | 14 | * GNU General Public License for more details. |
paul@37 | 15 | * |
paul@37 | 16 | * You should have received a copy of the GNU General Public License |
paul@37 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@37 | 18 | */ |
paul@37 | 19 | |
paul@37 | 20 | |
paul@37 | 21 | #include "pic32_c.h" |
paul@37 | 22 | #include "init.h" |
paul@37 | 23 | #include "debug.h" |
paul@37 | 24 | #include "main.h" |
paul@37 | 25 | #include "vga.h" |
paul@37 | 26 | |
paul@37 | 27 | |
paul@37 | 28 | |
paul@37 | 29 | /* Display state. */ |
paul@37 | 30 | |
paul@37 | 31 | static void (*state_handler)(void); |
paul@37 | 32 | static uint32_t line; |
paul@37 | 33 | |
paul@37 | 34 | /* Pixel data. */ |
paul@37 | 35 | |
paul@37 | 36 | static uint8_t linedata[LINE_LENGTH]; |
paul@37 | 37 | static const uint8_t zerodata[ZERO_LENGTH] = {0}; |
paul@37 | 38 | |
paul@37 | 39 | |
paul@37 | 40 | |
paul@37 | 41 | static void test_linedata(void) |
paul@37 | 42 | { |
paul@37 | 43 | int i; |
paul@37 | 44 | |
paul@37 | 45 | for (i = 0; i < LINE_LENGTH; i++) |
paul@37 | 46 | linedata[i] = (i % 2) ? 0xff : 0x00; |
paul@37 | 47 | } |
paul@37 | 48 | |
paul@37 | 49 | /* Blink an attached LED with delays implemented using a loop. */ |
paul@37 | 50 | |
paul@37 | 51 | static void blink(uint32_t delay, uint32_t port, uint32_t pins) |
paul@37 | 52 | { |
paul@37 | 53 | uint32_t counter; |
paul@37 | 54 | |
paul@37 | 55 | /* Clear outputs (LED). */ |
paul@37 | 56 | |
paul@37 | 57 | CLR_REG(port, pins); |
paul@37 | 58 | |
paul@37 | 59 | while (1) |
paul@37 | 60 | { |
paul@37 | 61 | counter = delay; |
paul@37 | 62 | |
paul@37 | 63 | while (counter--) __asm__(""); /* retain loop */ |
paul@37 | 64 | |
paul@37 | 65 | /* Invert outputs (LED). */ |
paul@37 | 66 | |
paul@37 | 67 | INV_REG(port, pins); |
paul@37 | 68 | } |
paul@37 | 69 | } |
paul@37 | 70 | |
paul@37 | 71 | |
paul@37 | 72 | |
paul@37 | 73 | /* Main program. */ |
paul@37 | 74 | |
paul@37 | 75 | void main(void) |
paul@37 | 76 | { |
paul@37 | 77 | line = 0; |
paul@37 | 78 | state_handler = vbp_active; |
paul@37 | 79 | test_linedata(); |
paul@37 | 80 | |
paul@37 | 81 | init_memory(); |
paul@37 | 82 | init_pins(); |
paul@37 | 83 | init_outputs(); |
paul@37 | 84 | |
paul@37 | 85 | unlock_config(); |
paul@37 | 86 | config_oc(); |
paul@37 | 87 | config_uart(); |
paul@37 | 88 | lock_config(); |
paul@37 | 89 | |
paul@37 | 90 | init_dma(); |
paul@37 | 91 | |
paul@37 | 92 | /* Peripheral relationships: |
paul@37 | 93 | |
paul@37 | 94 | Timer2 -> OC1 |
paul@37 | 95 | -> OC2 (vertical sync region) |
paul@37 | 96 | -> DMA0: zerodata -> PORTB (visible region) |
paul@37 | 97 | | |
paul@37 | 98 | Timer3 -> DMA1: linedata -> PORTB |
paul@37 | 99 | | |
paul@37 | 100 | DMA1 -> DMA2: zerodata -> PORTB |
paul@37 | 101 | */ |
paul@37 | 102 | |
paul@37 | 103 | /* Initiate DMA on the Timer2 interrupt condition, transferring line data to |
paul@37 | 104 | the first byte of PORTB. Do not enable the channel for initiation until |
paul@37 | 105 | the visible region is about to start. */ |
paul@37 | 106 | |
paul@37 | 107 | dma_init(0, 3); |
paul@37 | 108 | dma_set_auto_enable(0, 1); |
paul@37 | 109 | dma_set_interrupt(0, T2, 1); |
paul@37 | 110 | dma_set_transfer(0, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH, |
paul@37 | 111 | HW_PHYSICAL(PORTB), 1, |
paul@37 | 112 | ZERO_LENGTH); |
paul@37 | 113 | |
paul@37 | 114 | /* Enable DMA on the preceding channel's completion, with the Timer3 |
paul@37 | 115 | interrupt condition initiating transfers. */ |
paul@37 | 116 | |
paul@37 | 117 | dma_init(1, 3); |
paul@37 | 118 | dma_set_chaining(1, dma_chain_previous); |
paul@37 | 119 | dma_set_interrupt(1, T3, 1); |
paul@37 | 120 | dma_set_transfer(1, PHYSICAL((uint32_t) linedata), LINE_LENGTH, |
paul@37 | 121 | HW_PHYSICAL(PORTB), 1, |
paul@37 | 122 | 1); |
paul@37 | 123 | dma_init_interrupt(1, 0b00001000, 1, 3); |
paul@37 | 124 | |
paul@37 | 125 | /* Enable DMA on the preceding channel's completion, with this also |
paul@37 | 126 | initiating transfers. */ |
paul@37 | 127 | |
paul@37 | 128 | dma_init(2, 3); |
paul@37 | 129 | dma_set_chaining(2, dma_chain_previous); |
paul@37 | 130 | dma_set_interrupt(2, DMA1, 1); |
paul@37 | 131 | dma_set_transfer(2, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH, |
paul@37 | 132 | HW_PHYSICAL(PORTB), 1, |
paul@37 | 133 | ZERO_LENGTH); |
paul@37 | 134 | dma_set_receive_events(2, 1); |
paul@37 | 135 | |
paul@37 | 136 | /* Configure a timer for the horizontal sync. The timer has no prescaling |
paul@37 | 137 | (0). */ |
paul@37 | 138 | |
paul@37 | 139 | timer_init(2, 0, HFREQ_LIMIT); |
paul@37 | 140 | timer_on(2); |
paul@37 | 141 | |
paul@37 | 142 | /* Configure a timer for line data transfers. */ |
paul@37 | 143 | |
paul@37 | 144 | timer_init(3, 0, 1); |
paul@37 | 145 | timer_on(3); |
paul@37 | 146 | |
paul@37 | 147 | /* Horizontal sync. */ |
paul@37 | 148 | |
paul@37 | 149 | /* Configure output compare in dual compare (continuous output) mode using |
paul@37 | 150 | Timer2 as time base. The interrupt condition drives the first DMA channel |
paul@37 | 151 | and is handled to drive the display state machine. */ |
paul@37 | 152 | |
paul@37 | 153 | oc_init(1, 0b101, 2); |
paul@37 | 154 | oc_set_pulse(1, HSYNC_END); |
paul@37 | 155 | oc_set_pulse_end(1, HSYNC_START); |
paul@37 | 156 | oc_init_interrupt(1, 7, 3); |
paul@37 | 157 | oc_on(1); |
paul@37 | 158 | |
paul@37 | 159 | /* Vertical sync. */ |
paul@37 | 160 | |
paul@37 | 161 | /* Configure output compare in single compare (output driven low) mode using |
paul@37 | 162 | Timer2 as time base. The unit is enabled later. It is only really used to |
paul@37 | 163 | achieve precisely-timed level transitions in hardware. */ |
paul@37 | 164 | |
paul@37 | 165 | oc_init(2, 0b010, 2); |
paul@37 | 166 | oc_set_pulse(2, 0); |
paul@37 | 167 | |
paul@37 | 168 | uart_init(1, 115200); |
paul@37 | 169 | uart_on(1); |
paul@37 | 170 | |
paul@37 | 171 | interrupts_on(); |
paul@37 | 172 | |
paul@37 | 173 | blink(3 << 24, PORTA, 1 << 3); |
paul@37 | 174 | } |
paul@37 | 175 | |
paul@37 | 176 | |
paul@37 | 177 | |
paul@37 | 178 | /* Exception and interrupt handlers. */ |
paul@37 | 179 | |
paul@37 | 180 | void exception_handler(void) |
paul@37 | 181 | { |
paul@37 | 182 | blink(3 << 12, PORTA, 1 << 3); |
paul@37 | 183 | } |
paul@37 | 184 | |
paul@37 | 185 | void interrupt_handler(void) |
paul@37 | 186 | { |
paul@37 | 187 | uint32_t ifs; |
paul@37 | 188 | |
paul@37 | 189 | /* Check for a OC1 interrupt condition. */ |
paul@37 | 190 | |
paul@37 | 191 | ifs = REG(OCIFS) & OC_INT_FLAGS(1, OCxIF); |
paul@37 | 192 | |
paul@37 | 193 | if (ifs) |
paul@37 | 194 | { |
paul@37 | 195 | line += 1; |
paul@37 | 196 | state_handler(); |
paul@37 | 197 | CLR_REG(OCIFS, ifs); |
paul@37 | 198 | } |
paul@37 | 199 | } |
paul@37 | 200 | |
paul@37 | 201 | |
paul@37 | 202 | |
paul@37 | 203 | /* Vertical back porch region. */ |
paul@37 | 204 | |
paul@37 | 205 | void vbp_active(void) |
paul@37 | 206 | { |
paul@37 | 207 | if (line < VISIBLE_START) |
paul@37 | 208 | return; |
paul@37 | 209 | |
paul@37 | 210 | /* Enter the visible region. */ |
paul@37 | 211 | |
paul@37 | 212 | state_handler = visible_active; |
paul@37 | 213 | |
paul@37 | 214 | /* NOTE: Set the line address. */ |
paul@37 | 215 | |
paul@37 | 216 | /* Enable the channel for the next line. */ |
paul@37 | 217 | |
paul@37 | 218 | dma_on(0); |
paul@37 | 219 | } |
paul@37 | 220 | |
paul@37 | 221 | /* Visible region. */ |
paul@37 | 222 | |
paul@37 | 223 | void visible_active(void) |
paul@37 | 224 | { |
paul@37 | 225 | uint32_t ifs; |
paul@37 | 226 | |
paul@37 | 227 | /* Remove any DMA interrupt condition (CHBCIF). */ |
paul@37 | 228 | |
paul@37 | 229 | ifs = REG(DMAIFS) & DMA_INT_FLAGS(1, DCHxIF); |
paul@37 | 230 | |
paul@37 | 231 | if (ifs) |
paul@37 | 232 | { |
paul@37 | 233 | CLR_REG(DMA_REG(1, DCHxINT), 0b11111111); |
paul@37 | 234 | CLR_REG(DMAIFS, ifs); |
paul@37 | 235 | INV_REG(PORTA, 1 << 2); |
paul@37 | 236 | } |
paul@37 | 237 | |
paul@37 | 238 | if (line < VFP_START) |
paul@37 | 239 | { |
paul@37 | 240 | /* NOTE: Update the line address and handle wraparound. */ |
paul@37 | 241 | |
paul@37 | 242 | return; |
paul@37 | 243 | } |
paul@37 | 244 | |
paul@37 | 245 | /* End the visible region. */ |
paul@37 | 246 | |
paul@37 | 247 | state_handler = vfp_active; |
paul@37 | 248 | |
paul@37 | 249 | /* Disable the channel for the next line. */ |
paul@37 | 250 | |
paul@37 | 251 | dma_off(0); |
paul@37 | 252 | } |
paul@37 | 253 | |
paul@37 | 254 | /* Vertical front porch region. */ |
paul@37 | 255 | |
paul@37 | 256 | void vfp_active(void) |
paul@37 | 257 | { |
paul@37 | 258 | if (line < VSYNC_START) |
paul@37 | 259 | return; |
paul@37 | 260 | |
paul@37 | 261 | /* Enter the vertical sync region. */ |
paul@37 | 262 | |
paul@37 | 263 | state_handler = vsync_active; |
paul@37 | 264 | |
paul@37 | 265 | /* Bring vsync low (single compare, output driven low) when the next line |
paul@37 | 266 | starts. */ |
paul@37 | 267 | |
paul@37 | 268 | oc_init(2, 0b010, 2); |
paul@37 | 269 | oc_on(2); |
paul@37 | 270 | } |
paul@37 | 271 | |
paul@37 | 272 | /* Vertical sync region. */ |
paul@37 | 273 | |
paul@37 | 274 | void vsync_active(void) |
paul@37 | 275 | { |
paul@37 | 276 | if (line < VSYNC_END) |
paul@37 | 277 | return; |
paul@37 | 278 | |
paul@37 | 279 | /* Start again at the top of the display. */ |
paul@37 | 280 | |
paul@37 | 281 | line = 0; |
paul@37 | 282 | state_handler = vbp_active; |
paul@37 | 283 | |
paul@37 | 284 | /* Bring vsync high (single compare, output driven high) when the next line |
paul@37 | 285 | starts. */ |
paul@37 | 286 | |
paul@37 | 287 | oc_init(2, 0b001, 2); |
paul@37 | 288 | oc_on(2); |
paul@37 | 289 | } |
paul@37 | 290 | |
paul@37 | 291 | |
paul@37 | 292 | |
paul@37 | 293 | /* Peripheral pin configuration. */ |
paul@37 | 294 | |
paul@37 | 295 | void config_oc(void) |
paul@37 | 296 | { |
paul@37 | 297 | /* Map OC1 to RPA0. */ |
paul@37 | 298 | |
paul@37 | 299 | REG(RPA0R) = 0b0101; /* RPA0R<3:0> = 0101 (OC1) */ |
paul@37 | 300 | |
paul@37 | 301 | /* Map OC2 to RPA1. */ |
paul@37 | 302 | |
paul@37 | 303 | REG(RPA1R) = 0b0101; /* RPA1R<3:0> = 0101 (OC2) */ |
paul@37 | 304 | } |
paul@37 | 305 | |
paul@37 | 306 | void config_uart(void) |
paul@37 | 307 | { |
paul@37 | 308 | /* Map U1RX to RPB13. */ |
paul@37 | 309 | |
paul@37 | 310 | REG(U1RXR) = 0b0011; /* U1RXR<3:0> = 0011 (RPB13) */ |
paul@37 | 311 | |
paul@37 | 312 | /* Map U1TX to RPB15. */ |
paul@37 | 313 | |
paul@37 | 314 | REG(RPB15R) = 0b0001; /* RPB15R<3:0> = 0001 (U1TX) */ |
paul@37 | 315 | |
paul@37 | 316 | /* Set RPB13 to input. */ |
paul@37 | 317 | |
paul@37 | 318 | SET_REG(TRISB, 1 << 13); |
paul@37 | 319 | } |