paul@35 | 1 | /* |
paul@35 | 2 | * Generate a VGA signal using a PIC32 microcontroller. |
paul@35 | 3 | * |
paul@35 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@35 | 5 | * |
paul@35 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@35 | 7 | * it under the terms of the GNU General Public License as published by |
paul@35 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@35 | 9 | * (at your option) any later version. |
paul@35 | 10 | * |
paul@35 | 11 | * This program is distributed in the hope that it will be useful, |
paul@35 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@35 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@35 | 14 | * GNU General Public License for more details. |
paul@35 | 15 | * |
paul@35 | 16 | * You should have received a copy of the GNU General Public License |
paul@35 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@35 | 18 | */ |
paul@35 | 19 | |
paul@35 | 20 | |
paul@35 | 21 | #include "pic32_c.h" |
paul@35 | 22 | #include "init.h" |
paul@35 | 23 | #include "debug.h" |
paul@47 | 24 | |
paul@47 | 25 | /* Specific functionality. */ |
paul@47 | 26 | |
paul@35 | 27 | #include "main.h" |
paul@47 | 28 | #include "devconfig.h" |
paul@35 | 29 | #include "vga.h" |
paul@48 | 30 | #include "display.h" |
paul@49 | 31 | #include "display_config.h" |
paul@35 | 32 | |
paul@35 | 33 | |
paul@35 | 34 | |
paul@35 | 35 | /* Display state. */ |
paul@35 | 36 | |
paul@35 | 37 | static void (*state_handler)(void); |
paul@35 | 38 | static uint32_t line; |
paul@35 | 39 | |
paul@48 | 40 | /* Pointers to pixel lines. */ |
paul@48 | 41 | |
paul@49 | 42 | static uint8_t *linedata; |
paul@48 | 43 | |
paul@35 | 44 | /* Pixel data. */ |
paul@35 | 45 | |
paul@35 | 46 | static const uint8_t zerodata[ZERO_LENGTH] = {0}; |
paul@35 | 47 | |
paul@35 | 48 | |
paul@35 | 49 | |
paul@35 | 50 | /* Blink an attached LED with delays implemented using a loop. */ |
paul@35 | 51 | |
paul@35 | 52 | static void blink(uint32_t delay, uint32_t port, uint32_t pins) |
paul@35 | 53 | { |
paul@35 | 54 | uint32_t counter; |
paul@35 | 55 | |
paul@35 | 56 | /* Clear outputs (LED). */ |
paul@35 | 57 | |
paul@35 | 58 | CLR_REG(port, pins); |
paul@35 | 59 | |
paul@35 | 60 | while (1) |
paul@35 | 61 | { |
paul@35 | 62 | counter = delay; |
paul@35 | 63 | |
paul@35 | 64 | while (counter--) __asm__(""); /* retain loop */ |
paul@35 | 65 | |
paul@35 | 66 | /* Invert outputs (LED). */ |
paul@35 | 67 | |
paul@35 | 68 | INV_REG(port, pins); |
paul@35 | 69 | } |
paul@35 | 70 | } |
paul@35 | 71 | |
paul@35 | 72 | |
paul@35 | 73 | |
paul@35 | 74 | /* Main program. */ |
paul@35 | 75 | |
paul@35 | 76 | void main(void) |
paul@35 | 77 | { |
paul@35 | 78 | line = 0; |
paul@35 | 79 | state_handler = vbp_active; |
paul@49 | 80 | test_linedata(&display_config); |
paul@35 | 81 | |
paul@35 | 82 | init_memory(); |
paul@35 | 83 | init_pins(); |
paul@35 | 84 | init_outputs(); |
paul@35 | 85 | |
paul@35 | 86 | unlock_config(); |
paul@35 | 87 | config_oc(); |
paul@35 | 88 | config_uart(); |
paul@35 | 89 | lock_config(); |
paul@35 | 90 | |
paul@35 | 91 | init_dma(); |
paul@35 | 92 | init_pm(); |
paul@35 | 93 | |
paul@35 | 94 | /* Configure parallel master mode. */ |
paul@35 | 95 | |
paul@35 | 96 | pm_init(0, 0b10); |
paul@35 | 97 | pm_set_output(0, 1, 0); |
paul@35 | 98 | pm_on(0); |
paul@35 | 99 | |
paul@35 | 100 | /* Initiate DMA on the Timer2 interrupt transferring line data to the first |
paul@35 | 101 | byte of PORTB. Do not enable the channel for initiation until the visible |
paul@35 | 102 | region is about to start. */ |
paul@35 | 103 | |
paul@35 | 104 | dma_init(0, 3); |
paul@35 | 105 | dma_set_auto_enable(0, 1); |
paul@35 | 106 | dma_set_interrupt(0, T2, 1); |
paul@49 | 107 | dma_set_transfer(0, PHYSICAL((uint32_t) linedata), display_config.line_length, |
paul@35 | 108 | HW_PHYSICAL(PM_REG(0, PMxDIN)), 1, |
paul@45 | 109 | TRANSFER_CELL_SIZE); |
paul@35 | 110 | |
paul@48 | 111 | /* Enable DMA on the preceding channel's completion, with the timer event |
paul@48 | 112 | initiating the transfer. This "reset" or "zero" transfer is employed to |
paul@48 | 113 | set the pixel level to black in a connected flip-flop. Without the |
paul@48 | 114 | flip-flop it is superfluous. */ |
paul@35 | 115 | |
paul@35 | 116 | dma_init(1, 3); |
paul@35 | 117 | dma_set_chaining(1, dma_chain_previous); |
paul@48 | 118 | dma_set_interrupt(1, T2, 1); |
paul@35 | 119 | dma_set_transfer(1, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH, |
paul@35 | 120 | HW_PHYSICAL(PM_REG(0, PMxDIN)), 1, |
paul@35 | 121 | ZERO_LENGTH); |
paul@35 | 122 | dma_set_receive_events(1, 1); |
paul@35 | 123 | |
paul@35 | 124 | /* Configure a timer for the horizontal sync. The timer has no prescaling |
paul@35 | 125 | (0). */ |
paul@35 | 126 | |
paul@35 | 127 | timer_init(2, 0, HFREQ_LIMIT); |
paul@35 | 128 | timer_on(2); |
paul@35 | 129 | |
paul@35 | 130 | /* Horizontal sync. */ |
paul@35 | 131 | |
paul@35 | 132 | /* Configure output compare in dual compare (continuous output) mode using |
paul@35 | 133 | Timer2 as time base. The interrupt condition drives the first DMA channel |
paul@35 | 134 | and is handled to drive the display state machine. */ |
paul@35 | 135 | |
paul@35 | 136 | oc_init(1, 0b101, 2); |
paul@35 | 137 | oc_set_pulse(1, HSYNC_END); |
paul@35 | 138 | oc_set_pulse_end(1, HSYNC_START); |
paul@35 | 139 | oc_init_interrupt(1, 7, 3); |
paul@35 | 140 | oc_on(1); |
paul@35 | 141 | |
paul@35 | 142 | /* Vertical sync. */ |
paul@35 | 143 | |
paul@35 | 144 | /* Configure output compare in single compare (output driven low) mode using |
paul@35 | 145 | Timer2 as time base. The unit is enabled later. It is only really used to |
paul@35 | 146 | achieve precisely-timed level transitions in hardware. */ |
paul@35 | 147 | |
paul@35 | 148 | oc_init(2, 0b010, 2); |
paul@35 | 149 | oc_set_pulse(2, 0); |
paul@35 | 150 | |
paul@47 | 151 | uart_init(1, FPB, 115200); |
paul@35 | 152 | uart_on(1); |
paul@35 | 153 | |
paul@35 | 154 | interrupts_on(); |
paul@35 | 155 | |
paul@35 | 156 | blink(3 << 24, PORTA, 1 << 2); |
paul@35 | 157 | } |
paul@35 | 158 | |
paul@35 | 159 | |
paul@35 | 160 | |
paul@35 | 161 | /* Exception and interrupt handlers. */ |
paul@35 | 162 | |
paul@35 | 163 | void exception_handler(void) |
paul@35 | 164 | { |
paul@35 | 165 | blink(3 << 12, PORTA, 1 << 2); |
paul@35 | 166 | } |
paul@35 | 167 | |
paul@35 | 168 | void interrupt_handler(void) |
paul@35 | 169 | { |
paul@35 | 170 | uint32_t ifs; |
paul@35 | 171 | |
paul@35 | 172 | /* Check for a OC1 interrupt condition. */ |
paul@35 | 173 | |
paul@35 | 174 | ifs = REG(OCIFS) & OC_INT_FLAGS(1, OCxIF); |
paul@35 | 175 | |
paul@35 | 176 | if (ifs) |
paul@35 | 177 | { |
paul@35 | 178 | line += 1; |
paul@35 | 179 | state_handler(); |
paul@35 | 180 | CLR_REG(OCIFS, ifs); |
paul@35 | 181 | } |
paul@35 | 182 | } |
paul@35 | 183 | |
paul@35 | 184 | |
paul@35 | 185 | |
paul@35 | 186 | /* Vertical back porch region. */ |
paul@35 | 187 | |
paul@35 | 188 | void vbp_active(void) |
paul@35 | 189 | { |
paul@35 | 190 | if (line < VISIBLE_START) |
paul@35 | 191 | return; |
paul@35 | 192 | |
paul@35 | 193 | /* Enter the visible region. */ |
paul@35 | 194 | |
paul@35 | 195 | state_handler = visible_active; |
paul@35 | 196 | |
paul@48 | 197 | /* Set the line address. */ |
paul@48 | 198 | |
paul@49 | 199 | linedata = display_config.screen_start; |
paul@49 | 200 | dma_set_source(0, PHYSICAL((uint32_t) linedata), display_config.line_length); |
paul@35 | 201 | |
paul@35 | 202 | /* Enable the channel for the next line. */ |
paul@35 | 203 | |
paul@35 | 204 | dma_on(0); |
paul@35 | 205 | } |
paul@35 | 206 | |
paul@35 | 207 | /* Visible region. */ |
paul@35 | 208 | |
paul@35 | 209 | void visible_active(void) |
paul@35 | 210 | { |
paul@35 | 211 | if (line < VFP_START) |
paul@35 | 212 | { |
paul@48 | 213 | /* Update the line address and handle wraparound. */ |
paul@35 | 214 | |
paul@49 | 215 | if (!(line % display_config.line_multiplier)) |
paul@48 | 216 | { |
paul@49 | 217 | linedata += display_config.line_length; |
paul@49 | 218 | if (linedata >= display_config.screen_limit) |
paul@49 | 219 | linedata -= display_config.screen_size; |
paul@48 | 220 | } |
paul@48 | 221 | |
paul@49 | 222 | dma_set_source(0, PHYSICAL((uint32_t) linedata), display_config.line_length); |
paul@35 | 223 | return; |
paul@35 | 224 | } |
paul@35 | 225 | |
paul@35 | 226 | /* End the visible region. */ |
paul@35 | 227 | |
paul@35 | 228 | state_handler = vfp_active; |
paul@35 | 229 | |
paul@35 | 230 | /* Disable the channel for the next line. */ |
paul@35 | 231 | |
paul@35 | 232 | dma_off(0); |
paul@35 | 233 | } |
paul@35 | 234 | |
paul@35 | 235 | /* Vertical front porch region. */ |
paul@35 | 236 | |
paul@35 | 237 | void vfp_active(void) |
paul@35 | 238 | { |
paul@35 | 239 | if (line < VSYNC_START) |
paul@35 | 240 | return; |
paul@35 | 241 | |
paul@35 | 242 | /* Enter the vertical sync region. */ |
paul@35 | 243 | |
paul@35 | 244 | state_handler = vsync_active; |
paul@35 | 245 | |
paul@35 | 246 | /* Bring vsync low (single compare, output driven low) when the next line |
paul@35 | 247 | starts. */ |
paul@35 | 248 | |
paul@35 | 249 | oc_init(2, 0b010, 2); |
paul@35 | 250 | oc_on(2); |
paul@35 | 251 | } |
paul@35 | 252 | |
paul@35 | 253 | /* Vertical sync region. */ |
paul@35 | 254 | |
paul@35 | 255 | void vsync_active(void) |
paul@35 | 256 | { |
paul@35 | 257 | if (line < VSYNC_END) |
paul@35 | 258 | return; |
paul@35 | 259 | |
paul@35 | 260 | /* Start again at the top of the display. */ |
paul@35 | 261 | |
paul@35 | 262 | line = 0; |
paul@35 | 263 | state_handler = vbp_active; |
paul@35 | 264 | |
paul@35 | 265 | /* Bring vsync high (single compare, output driven high) when the next line |
paul@35 | 266 | starts. */ |
paul@35 | 267 | |
paul@35 | 268 | oc_init(2, 0b001, 2); |
paul@35 | 269 | oc_on(2); |
paul@35 | 270 | } |
paul@35 | 271 | |
paul@35 | 272 | |
paul@35 | 273 | |
paul@35 | 274 | /* Peripheral pin configuration. */ |
paul@35 | 275 | |
paul@35 | 276 | void config_oc(void) |
paul@35 | 277 | { |
paul@35 | 278 | /* Map OC1 to RPB4. */ |
paul@35 | 279 | |
paul@35 | 280 | REG(RPB4R) = 0b0101; /* RPB4R<3:0> = 0101 (OC1) */ |
paul@35 | 281 | |
paul@35 | 282 | /* Map OC2 to RPB5. */ |
paul@35 | 283 | |
paul@35 | 284 | REG(RPB5R) = 0b0101; /* RPB5R<3:0> = 0101 (OC2) */ |
paul@35 | 285 | } |
paul@35 | 286 | |
paul@35 | 287 | void config_uart(void) |
paul@35 | 288 | { |
paul@35 | 289 | /* Map U1RX to RPB13. */ |
paul@35 | 290 | |
paul@35 | 291 | REG(U1RXR) = 0b0011; /* U1RXR<3:0> = 0011 (RPB13) */ |
paul@35 | 292 | |
paul@35 | 293 | /* Map U1TX to RPB15. */ |
paul@35 | 294 | |
paul@35 | 295 | REG(RPB15R) = 0b0001; /* RPB15R<3:0> = 0001 (U1TX) */ |
paul@35 | 296 | |
paul@35 | 297 | /* Set RPB13 to input. */ |
paul@35 | 298 | |
paul@35 | 299 | SET_REG(TRISB, 1 << 13); |
paul@35 | 300 | } |