paul@37 | 1 | /* |
paul@37 | 2 | * Generate a VGA signal using a PIC32 microcontroller. |
paul@37 | 3 | * |
paul@37 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@37 | 5 | * |
paul@37 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@37 | 7 | * it under the terms of the GNU General Public License as published by |
paul@37 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@37 | 9 | * (at your option) any later version. |
paul@37 | 10 | * |
paul@37 | 11 | * This program is distributed in the hope that it will be useful, |
paul@37 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@37 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@37 | 14 | * GNU General Public License for more details. |
paul@37 | 15 | * |
paul@37 | 16 | * You should have received a copy of the GNU General Public License |
paul@37 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@37 | 18 | */ |
paul@37 | 19 | |
paul@37 | 20 | |
paul@37 | 21 | #include "pic32_c.h" |
paul@37 | 22 | #include "init.h" |
paul@37 | 23 | #include "debug.h" |
paul@41 | 24 | |
paul@41 | 25 | /* Specific functionality. */ |
paul@41 | 26 | |
paul@37 | 27 | #include "main.h" |
paul@47 | 28 | #include "devconfig.h" |
paul@37 | 29 | #include "vga.h" |
paul@41 | 30 | #include "display.h" |
paul@49 | 31 | #include "display_config.h" |
paul@37 | 32 | |
paul@37 | 33 | |
paul@37 | 34 | |
paul@37 | 35 | /* Display state. */ |
paul@37 | 36 | |
paul@37 | 37 | static void (*state_handler)(void); |
paul@37 | 38 | static uint32_t line; |
paul@37 | 39 | |
paul@41 | 40 | /* Pointers to pixel lines. */ |
paul@41 | 41 | |
paul@49 | 42 | static uint8_t *linedata; |
paul@41 | 43 | |
paul@37 | 44 | /* Pixel data. */ |
paul@37 | 45 | |
paul@37 | 46 | static const uint8_t zerodata[ZERO_LENGTH] = {0}; |
paul@37 | 47 | |
paul@37 | 48 | |
paul@37 | 49 | |
paul@37 | 50 | /* Blink an attached LED with delays implemented using a loop. */ |
paul@37 | 51 | |
paul@37 | 52 | static void blink(uint32_t delay, uint32_t port, uint32_t pins) |
paul@37 | 53 | { |
paul@37 | 54 | uint32_t counter; |
paul@37 | 55 | |
paul@37 | 56 | /* Clear outputs (LED). */ |
paul@37 | 57 | |
paul@37 | 58 | CLR_REG(port, pins); |
paul@37 | 59 | |
paul@37 | 60 | while (1) |
paul@37 | 61 | { |
paul@37 | 62 | counter = delay; |
paul@37 | 63 | |
paul@37 | 64 | while (counter--) __asm__(""); /* retain loop */ |
paul@37 | 65 | |
paul@37 | 66 | /* Invert outputs (LED). */ |
paul@37 | 67 | |
paul@37 | 68 | INV_REG(port, pins); |
paul@37 | 69 | } |
paul@37 | 70 | } |
paul@37 | 71 | |
paul@37 | 72 | |
paul@37 | 73 | |
paul@37 | 74 | /* Main program. */ |
paul@37 | 75 | |
paul@37 | 76 | void main(void) |
paul@37 | 77 | { |
paul@37 | 78 | line = 0; |
paul@37 | 79 | state_handler = vbp_active; |
paul@49 | 80 | test_linedata(&display_config); |
paul@37 | 81 | |
paul@37 | 82 | init_memory(); |
paul@37 | 83 | init_pins(); |
paul@37 | 84 | init_outputs(); |
paul@37 | 85 | |
paul@37 | 86 | unlock_config(); |
paul@37 | 87 | config_oc(); |
paul@37 | 88 | config_uart(); |
paul@37 | 89 | lock_config(); |
paul@37 | 90 | |
paul@37 | 91 | init_dma(); |
paul@37 | 92 | |
paul@37 | 93 | /* Peripheral relationships: |
paul@37 | 94 | |
paul@37 | 95 | Timer2 -> OC1 |
paul@37 | 96 | -> OC2 (vertical sync region) |
paul@46 | 97 | -> DMA1: zerodata -> PORTB (visible region) |
paul@37 | 98 | | |
paul@46 | 99 | Timer3 -> DMA0: linedata -> PORTB |
paul@46 | 100 | Timer3 -> DMA2: linedata -> PORTB |
paul@37 | 101 | | |
paul@46 | 102 | Timer3 -> DMA3: zerodata -> PORTB |
paul@37 | 103 | */ |
paul@37 | 104 | |
paul@37 | 105 | /* Initiate DMA on the Timer2 interrupt condition, transferring line data to |
paul@37 | 106 | the first byte of PORTB. Do not enable the channel for initiation until |
paul@37 | 107 | the visible region is about to start. */ |
paul@37 | 108 | |
paul@46 | 109 | dma_init(1, 3); |
paul@46 | 110 | dma_set_auto_enable(1, 1); |
paul@46 | 111 | dma_set_interrupt(1, T2, 1); |
paul@46 | 112 | dma_set_transfer(1, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH, |
paul@37 | 113 | HW_PHYSICAL(PORTB), 1, |
paul@37 | 114 | ZERO_LENGTH); |
paul@37 | 115 | |
paul@46 | 116 | /* Enable DMA on the zero channel's completion, with the Timer3 |
paul@37 | 117 | interrupt condition initiating transfers. */ |
paul@37 | 118 | |
paul@46 | 119 | dma_init(0, 3); |
paul@46 | 120 | dma_set_chaining(0, dma_chain_next); |
paul@46 | 121 | dma_set_interrupt(0, T3, 1); |
paul@49 | 122 | dma_set_transfer(0, PHYSICAL((uint32_t) display_config.screen_start), |
paul@49 | 123 | display_config.line_length / 2, |
paul@37 | 124 | HW_PHYSICAL(PORTB), 1, |
paul@46 | 125 | TRANSFER_CELL_SIZE); |
paul@46 | 126 | |
paul@46 | 127 | /* Enable DMA on the zero channel's completion, with the Timer3 |
paul@46 | 128 | interrupt condition initiating transfers. */ |
paul@46 | 129 | |
paul@46 | 130 | dma_init(2, 3); |
paul@46 | 131 | dma_set_chaining(2, dma_chain_previous); |
paul@46 | 132 | dma_set_interrupt(2, T3, 1); |
paul@49 | 133 | dma_set_transfer(2, PHYSICAL((uint32_t) display_config.screen_start + |
paul@49 | 134 | display_config.line_length / 2), |
paul@49 | 135 | display_config.line_length / 2, |
paul@46 | 136 | HW_PHYSICAL(PORTB), 1, |
paul@46 | 137 | TRANSFER_CELL_SIZE); |
paul@37 | 138 | |
paul@37 | 139 | /* Enable DMA on the preceding channel's completion, with this also |
paul@37 | 140 | initiating transfers. */ |
paul@37 | 141 | |
paul@46 | 142 | dma_init(3, 3); |
paul@46 | 143 | dma_set_chaining(3, dma_chain_previous); |
paul@46 | 144 | dma_set_interrupt(3, T3, 1); |
paul@46 | 145 | dma_set_transfer(3, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH, |
paul@37 | 146 | HW_PHYSICAL(PORTB), 1, |
paul@37 | 147 | ZERO_LENGTH); |
paul@46 | 148 | dma_set_receive_events(3, 1); |
paul@37 | 149 | |
paul@37 | 150 | /* Configure a timer for the horizontal sync. The timer has no prescaling |
paul@37 | 151 | (0). */ |
paul@37 | 152 | |
paul@37 | 153 | timer_init(2, 0, HFREQ_LIMIT); |
paul@37 | 154 | timer_on(2); |
paul@37 | 155 | |
paul@37 | 156 | /* Configure a timer for line data transfers. */ |
paul@37 | 157 | |
paul@37 | 158 | timer_init(3, 0, 1); |
paul@37 | 159 | timer_on(3); |
paul@37 | 160 | |
paul@37 | 161 | /* Horizontal sync. */ |
paul@37 | 162 | |
paul@37 | 163 | /* Configure output compare in dual compare (continuous output) mode using |
paul@37 | 164 | Timer2 as time base. The interrupt condition drives the first DMA channel |
paul@37 | 165 | and is handled to drive the display state machine. */ |
paul@37 | 166 | |
paul@37 | 167 | oc_init(1, 0b101, 2); |
paul@37 | 168 | oc_set_pulse(1, HSYNC_END); |
paul@37 | 169 | oc_set_pulse_end(1, HSYNC_START); |
paul@37 | 170 | oc_init_interrupt(1, 7, 3); |
paul@37 | 171 | oc_on(1); |
paul@37 | 172 | |
paul@37 | 173 | /* Vertical sync. */ |
paul@37 | 174 | |
paul@37 | 175 | /* Configure output compare in single compare (output driven low) mode using |
paul@37 | 176 | Timer2 as time base. The unit is enabled later. It is only really used to |
paul@37 | 177 | achieve precisely-timed level transitions in hardware. */ |
paul@37 | 178 | |
paul@37 | 179 | oc_init(2, 0b010, 2); |
paul@37 | 180 | oc_set_pulse(2, 0); |
paul@37 | 181 | |
paul@47 | 182 | uart_init(1, FPB, 115200); |
paul@37 | 183 | uart_on(1); |
paul@37 | 184 | |
paul@37 | 185 | interrupts_on(); |
paul@37 | 186 | |
paul@37 | 187 | blink(3 << 24, PORTA, 1 << 3); |
paul@37 | 188 | } |
paul@37 | 189 | |
paul@37 | 190 | |
paul@37 | 191 | |
paul@37 | 192 | /* Exception and interrupt handlers. */ |
paul@37 | 193 | |
paul@37 | 194 | void exception_handler(void) |
paul@37 | 195 | { |
paul@37 | 196 | blink(3 << 12, PORTA, 1 << 3); |
paul@37 | 197 | } |
paul@37 | 198 | |
paul@37 | 199 | void interrupt_handler(void) |
paul@37 | 200 | { |
paul@37 | 201 | uint32_t ifs; |
paul@37 | 202 | |
paul@37 | 203 | /* Check for a OC1 interrupt condition. */ |
paul@37 | 204 | |
paul@37 | 205 | ifs = REG(OCIFS) & OC_INT_FLAGS(1, OCxIF); |
paul@37 | 206 | |
paul@37 | 207 | if (ifs) |
paul@37 | 208 | { |
paul@37 | 209 | line += 1; |
paul@37 | 210 | state_handler(); |
paul@37 | 211 | CLR_REG(OCIFS, ifs); |
paul@37 | 212 | } |
paul@37 | 213 | } |
paul@37 | 214 | |
paul@37 | 215 | |
paul@37 | 216 | |
paul@37 | 217 | /* Vertical back porch region. */ |
paul@37 | 218 | |
paul@37 | 219 | void vbp_active(void) |
paul@37 | 220 | { |
paul@37 | 221 | if (line < VISIBLE_START) |
paul@37 | 222 | return; |
paul@37 | 223 | |
paul@37 | 224 | /* Enter the visible region. */ |
paul@37 | 225 | |
paul@37 | 226 | state_handler = visible_active; |
paul@37 | 227 | |
paul@41 | 228 | /* Set the line address. */ |
paul@41 | 229 | |
paul@49 | 230 | linedata = display_config.screen_start; |
paul@49 | 231 | dma_set_source(0, PHYSICAL((uint32_t) linedata), display_config.line_length / 2); |
paul@49 | 232 | dma_set_source(2, PHYSICAL((uint32_t) linedata + display_config.line_length / 2), |
paul@49 | 233 | display_config.line_length / 2); |
paul@37 | 234 | |
paul@46 | 235 | /* Enable the channels for the next line. */ |
paul@37 | 236 | |
paul@46 | 237 | dma_on(1); |
paul@37 | 238 | } |
paul@37 | 239 | |
paul@37 | 240 | /* Visible region. */ |
paul@37 | 241 | |
paul@37 | 242 | void visible_active(void) |
paul@37 | 243 | { |
paul@43 | 244 | INV_REG(PORTA, 1 << 2); |
paul@37 | 245 | |
paul@37 | 246 | if (line < VFP_START) |
paul@37 | 247 | { |
paul@41 | 248 | /* Update the line address and handle wraparound. */ |
paul@37 | 249 | |
paul@49 | 250 | if (!(line % display_config.line_multiplier)) |
paul@41 | 251 | { |
paul@49 | 252 | linedata += display_config.line_length; |
paul@49 | 253 | if (linedata >= display_config.screen_limit) |
paul@49 | 254 | linedata -= display_config.screen_size; |
paul@41 | 255 | } |
paul@41 | 256 | |
paul@49 | 257 | dma_set_source(0, PHYSICAL((uint32_t) linedata), display_config.line_length / 2); |
paul@49 | 258 | dma_set_source(2, PHYSICAL((uint32_t) linedata + display_config.line_length / 2), |
paul@49 | 259 | display_config.line_length / 2); |
paul@37 | 260 | return; |
paul@37 | 261 | } |
paul@37 | 262 | |
paul@37 | 263 | /* End the visible region. */ |
paul@37 | 264 | |
paul@37 | 265 | state_handler = vfp_active; |
paul@37 | 266 | |
paul@46 | 267 | /* Disable the channels for the next line. */ |
paul@37 | 268 | |
paul@46 | 269 | dma_off(1); |
paul@37 | 270 | } |
paul@37 | 271 | |
paul@37 | 272 | /* Vertical front porch region. */ |
paul@37 | 273 | |
paul@37 | 274 | void vfp_active(void) |
paul@37 | 275 | { |
paul@37 | 276 | if (line < VSYNC_START) |
paul@37 | 277 | return; |
paul@37 | 278 | |
paul@37 | 279 | /* Enter the vertical sync region. */ |
paul@37 | 280 | |
paul@37 | 281 | state_handler = vsync_active; |
paul@37 | 282 | |
paul@37 | 283 | /* Bring vsync low (single compare, output driven low) when the next line |
paul@37 | 284 | starts. */ |
paul@37 | 285 | |
paul@37 | 286 | oc_init(2, 0b010, 2); |
paul@37 | 287 | oc_on(2); |
paul@37 | 288 | } |
paul@37 | 289 | |
paul@37 | 290 | /* Vertical sync region. */ |
paul@37 | 291 | |
paul@37 | 292 | void vsync_active(void) |
paul@37 | 293 | { |
paul@37 | 294 | if (line < VSYNC_END) |
paul@37 | 295 | return; |
paul@37 | 296 | |
paul@37 | 297 | /* Start again at the top of the display. */ |
paul@37 | 298 | |
paul@37 | 299 | line = 0; |
paul@37 | 300 | state_handler = vbp_active; |
paul@37 | 301 | |
paul@37 | 302 | /* Bring vsync high (single compare, output driven high) when the next line |
paul@37 | 303 | starts. */ |
paul@37 | 304 | |
paul@37 | 305 | oc_init(2, 0b001, 2); |
paul@37 | 306 | oc_on(2); |
paul@37 | 307 | } |
paul@37 | 308 | |
paul@37 | 309 | |
paul@37 | 310 | |
paul@37 | 311 | /* Peripheral pin configuration. */ |
paul@37 | 312 | |
paul@37 | 313 | void config_oc(void) |
paul@37 | 314 | { |
paul@37 | 315 | /* Map OC1 to RPA0. */ |
paul@37 | 316 | |
paul@37 | 317 | REG(RPA0R) = 0b0101; /* RPA0R<3:0> = 0101 (OC1) */ |
paul@37 | 318 | |
paul@37 | 319 | /* Map OC2 to RPA1. */ |
paul@37 | 320 | |
paul@37 | 321 | REG(RPA1R) = 0b0101; /* RPA1R<3:0> = 0101 (OC2) */ |
paul@37 | 322 | } |
paul@37 | 323 | |
paul@37 | 324 | void config_uart(void) |
paul@37 | 325 | { |
paul@37 | 326 | /* Map U1RX to RPB13. */ |
paul@37 | 327 | |
paul@37 | 328 | REG(U1RXR) = 0b0011; /* U1RXR<3:0> = 0011 (RPB13) */ |
paul@37 | 329 | |
paul@37 | 330 | /* Map U1TX to RPB15. */ |
paul@37 | 331 | |
paul@37 | 332 | REG(RPB15R) = 0b0001; /* RPB15R<3:0> = 0001 (U1TX) */ |
paul@37 | 333 | |
paul@37 | 334 | /* Set RPB13 to input. */ |
paul@37 | 335 | |
paul@37 | 336 | SET_REG(TRISB, 1 << 13); |
paul@37 | 337 | } |