paul@15 | 1 | /* |
paul@15 | 2 | * PIC32 peripheral descriptions. |
paul@15 | 3 | * |
paul@15 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@15 | 5 | * |
paul@15 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@15 | 7 | * it under the terms of the GNU General Public License as published by |
paul@15 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@15 | 9 | * (at your option) any later version. |
paul@15 | 10 | * |
paul@15 | 11 | * This program is distributed in the hope that it will be useful, |
paul@15 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@15 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@15 | 14 | * GNU General Public License for more details. |
paul@15 | 15 | * |
paul@15 | 16 | * You should have received a copy of the GNU General Public License |
paul@15 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@15 | 18 | */ |
paul@15 | 19 | |
paul@0 | 20 | #ifndef __PIC32_H__ |
paul@0 | 21 | #define __PIC32_H__ |
paul@0 | 22 | |
paul@3 | 23 | /* Peripheral addresses. |
paul@3 | 24 | * See... |
paul@0 | 25 | * TABLE 4-1: SFR MEMORYMAP |
paul@0 | 26 | * TABLE 11-3: PORTA REGISTER MAP |
paul@0 | 27 | * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet |
paul@0 | 28 | */ |
paul@0 | 29 | |
paul@21 | 30 | #define OSCCON 0xBF80F000 |
paul@21 | 31 | #define REFOCON 0xBF80F020 |
paul@21 | 32 | #define REFOTRIM 0xBF80F030 |
paul@21 | 33 | #define CFGCON 0xBF80F200 |
paul@21 | 34 | #define SYSKEY 0xBF80F230 |
paul@0 | 35 | |
paul@29 | 36 | #define INT2R 0xBF80FA08 |
paul@21 | 37 | #define U1RXR 0xBF80FA50 |
paul@0 | 38 | |
paul@21 | 39 | #define RPA0R 0xBF80FB00 |
paul@21 | 40 | #define RPA1R 0xBF80FB04 |
paul@21 | 41 | #define RPA2R 0xBF80FB08 |
paul@21 | 42 | #define RPA3R 0xBF80FB0C |
paul@21 | 43 | #define RPA4R 0xBF80FB10 |
paul@21 | 44 | #define RPB0R 0xBF80FB2C |
paul@21 | 45 | #define RPB1R 0xBF80FB30 |
paul@21 | 46 | #define RPB2R 0xBF80FB34 |
paul@21 | 47 | #define RPB3R 0xBF80FB38 |
paul@21 | 48 | #define RPB4R 0xBF80FB3C |
paul@21 | 49 | #define RPB5R 0xBF80FB40 |
paul@21 | 50 | #define RPB10R 0xBF80FB54 |
paul@21 | 51 | #define RPB15R 0xBF80FB68 |
paul@0 | 52 | |
paul@21 | 53 | #define INTCON 0xBF881000 |
paul@21 | 54 | #define IFS0 0xBF881030 |
paul@21 | 55 | #define IFS1 0xBF881040 |
paul@21 | 56 | #define IEC0 0xBF881060 |
paul@21 | 57 | #define IEC1 0xBF881070 |
paul@29 | 58 | #define IPC0 0xBF881090 |
paul@21 | 59 | #define IPC1 0xBF8810A0 |
paul@21 | 60 | #define IPC2 0xBF8810B0 |
paul@21 | 61 | #define IPC3 0xBF8810C0 |
paul@21 | 62 | #define IPC4 0xBF8810D0 |
paul@21 | 63 | #define IPC5 0xBF8810E0 |
paul@21 | 64 | #define IPC6 0xBF8810F0 |
paul@21 | 65 | #define IPC7 0xBF881100 |
paul@21 | 66 | #define IPC8 0xBF881110 |
paul@21 | 67 | #define IPC9 0xBF881120 |
paul@21 | 68 | #define IPC10 0xBF881130 |
paul@0 | 69 | |
paul@21 | 70 | #define BMXCON 0xBF882000 |
paul@21 | 71 | #define BMXDKPBA 0xBF882010 |
paul@21 | 72 | #define BMXDUDBA 0xBF882020 |
paul@21 | 73 | #define BMXDUPBA 0xBF882030 |
paul@21 | 74 | #define BMXDRMSZ 0xBF882040 |
paul@0 | 75 | |
paul@21 | 76 | #define ANSELA 0xBF886000 |
paul@21 | 77 | #define TRISA 0xBF886010 |
paul@21 | 78 | #define PORTA 0xBF886020 |
paul@21 | 79 | #define LATA 0xBF886030 |
paul@21 | 80 | #define ODCA 0xBF886040 |
paul@21 | 81 | #define ANSELB 0xBF886100 |
paul@21 | 82 | #define TRISB 0xBF886110 |
paul@21 | 83 | #define PORTB 0xBF886120 |
paul@21 | 84 | #define LATB 0xBF886130 |
paul@21 | 85 | #define ODCB 0xBF886140 |
paul@0 | 86 | |
paul@34 | 87 | /* DEVCFG conveniences. */ |
paul@34 | 88 | |
paul@34 | 89 | #define DEVCFG1_UNUSED 0xff7fcbd8 /* exclude FWDTWINSZ, WINDIS, WDTPS, FCKSM, POSCMOD, IESO */ |
paul@34 | 90 | |
paul@34 | 91 | #define DEVCFG1_FWDTEN_OFF (0 << 23) |
paul@34 | 92 | #define DEVCFG1_FWDTEN_ON (1 << 23) |
paul@34 | 93 | |
paul@34 | 94 | #define DEVCFG1_FPBDIV_1 (0b00 << 12) |
paul@34 | 95 | #define DEVCFG1_FPBDIV_2 (0b01 << 12) |
paul@34 | 96 | #define DEVCFG1_FPBDIV_4 (0b10 << 12) |
paul@34 | 97 | #define DEVCFG1_FPBDIV_8 (0b11 << 12) |
paul@34 | 98 | |
paul@34 | 99 | #define DEVCFG1_OSCIOFNC_ON (0 << 10) |
paul@34 | 100 | #define DEVCFG1_OSCIOFNC_OFF (1 << 10) |
paul@34 | 101 | |
paul@34 | 102 | #define DEVCFG1_FSOSCEN_OFF (0 << 5) |
paul@34 | 103 | #define DEVCFG1_FSOSCEN_ON (1 << 5) |
paul@34 | 104 | |
paul@34 | 105 | #define DEVCFG1_FNOSC_FRC (0b000) |
paul@34 | 106 | #define DEVCFG1_FNOSC_FRCDIV_PLL (0b001) |
paul@34 | 107 | #define DEVCFG1_FNOSC_FRCDIV (0b111) |
paul@34 | 108 | |
paul@34 | 109 | #define DEVCFG2_UNUSED 0xfff8ff88 /* exclude UPLLEN, UPLLIDIV */ |
paul@34 | 110 | |
paul@34 | 111 | #define DEVCFG2_FPLLODIV_1 (0b000 << 16) |
paul@34 | 112 | #define DEVCFG2_FPLLODIV_2 (0b001 << 16) |
paul@34 | 113 | #define DEVCFG2_FPLLODIV_4 (0b010 << 16) |
paul@34 | 114 | #define DEVCFG2_FPLLODIV_8 (0b011 << 16) |
paul@34 | 115 | #define DEVCFG2_FPLLODIV_16 (0b100 << 16) |
paul@34 | 116 | #define DEVCFG2_FPLLODIV_32 (0b101 << 16) |
paul@34 | 117 | #define DEVCFG2_FPLLODIV_64 (0b110 << 16) |
paul@34 | 118 | #define DEVCFG2_FPLLODIV_128 (0b111 << 16) |
paul@34 | 119 | |
paul@34 | 120 | #define DEVCFG2_FPLLMUL_15 (0b000 << 4) |
paul@34 | 121 | #define DEVCFG2_FPLLMUL_16 (0b001 << 4) |
paul@34 | 122 | #define DEVCFG2_FPLLMUL_17 (0b010 << 4) |
paul@34 | 123 | #define DEVCFG2_FPLLMUL_18 (0b011 << 4) |
paul@34 | 124 | #define DEVCFG2_FPLLMUL_19 (0b100 << 4) |
paul@34 | 125 | #define DEVCFG2_FPLLMUL_20 (0b101 << 4) |
paul@34 | 126 | #define DEVCFG2_FPLLMUL_21 (0b110 << 4) |
paul@34 | 127 | #define DEVCFG2_FPLLMUL_24 (0b111 << 4) |
paul@34 | 128 | |
paul@34 | 129 | #define DEVCFG2_FPLLIDIV_1 (0b000) |
paul@34 | 130 | #define DEVCFG2_FPLLIDIV_2 (0b001) |
paul@34 | 131 | #define DEVCFG2_FPLLIDIV_3 (0b010) |
paul@34 | 132 | #define DEVCFG2_FPLLIDIV_4 (0b011) |
paul@34 | 133 | #define DEVCFG2_FPLLIDIV_5 (0b100) |
paul@34 | 134 | #define DEVCFG2_FPLLIDIV_6 (0b101) |
paul@34 | 135 | #define DEVCFG2_FPLLIDIV_10 (0b110) |
paul@34 | 136 | #define DEVCFG2_FPLLIDIV_12 (0b111) |
paul@34 | 137 | |
paul@3 | 138 | /* DMA conveniences. */ |
paul@3 | 139 | |
paul@21 | 140 | #define DMACON 0xBF883000 |
paul@21 | 141 | #define DCH0CON 0xBF883060 |
paul@21 | 142 | #define DCH1CON 0xBF883120 |
paul@21 | 143 | #define DCH2CON 0xBF8831E0 |
paul@21 | 144 | #define DCH3CON 0xBF8832A0 |
paul@3 | 145 | |
paul@21 | 146 | #define DCHMIN 0 |
paul@21 | 147 | #define DCHMAX 3 |
paul@21 | 148 | #define DCHBASE DCH0CON |
paul@21 | 149 | #define DCHSTEP (DCH1CON - DCH0CON) |
paul@3 | 150 | |
paul@21 | 151 | #define DCHxCON 0x00 |
paul@21 | 152 | #define DCHxECON 0x10 |
paul@21 | 153 | #define DCHxINT 0x20 |
paul@21 | 154 | #define DCHxSSA 0x30 |
paul@21 | 155 | #define DCHxDSA 0x40 |
paul@21 | 156 | #define DCHxSSIZ 0x50 |
paul@21 | 157 | #define DCHxDSIZ 0x60 |
paul@21 | 158 | #define DCHxSPTR 0x70 |
paul@21 | 159 | #define DCHxDPTR 0x80 |
paul@21 | 160 | #define DCHxCSIZ 0x90 |
paul@21 | 161 | #define DCHxCPTR 0xA0 |
paul@21 | 162 | #define DCHxDAT 0xB0 |
paul@3 | 163 | |
paul@21 | 164 | #define DMAIEC IEC1 |
paul@21 | 165 | |
paul@21 | 166 | #define DCHxIE 1 |
paul@21 | 167 | |
paul@21 | 168 | #define DMAIFS IFS1 |
paul@14 | 169 | |
paul@21 | 170 | #define DCHxIF 1 |
paul@21 | 171 | |
paul@21 | 172 | #define DMAINTBASE 28 |
paul@21 | 173 | |
paul@21 | 174 | #define DMAIPC IPC10 |
paul@21 | 175 | #define DCHIPCBASE 0 |
paul@21 | 176 | #define DCHIPCSTEP 8 |
paul@3 | 177 | |
paul@29 | 178 | /* External interrupt conveniences. */ |
paul@29 | 179 | |
paul@29 | 180 | #define INTMIN 0 |
paul@29 | 181 | #define INTMAX 4 |
paul@29 | 182 | |
paul@29 | 183 | #define INTIEC IEC0 |
paul@29 | 184 | |
paul@29 | 185 | #define INTxIE 1 |
paul@29 | 186 | |
paul@29 | 187 | #define INTIFS IFS0 |
paul@29 | 188 | |
paul@29 | 189 | #define INTxIF 1 |
paul@29 | 190 | |
paul@29 | 191 | #define INTINTBASE 3 |
paul@29 | 192 | #define INTINTSTEP 5 |
paul@29 | 193 | |
paul@29 | 194 | #define INT0IPC IPC0 |
paul@29 | 195 | #define INT1IPC IPC1 |
paul@29 | 196 | #define INT2IPC IPC2 |
paul@29 | 197 | #define INT3IPC IPC3 |
paul@29 | 198 | #define INT4IPC IPC4 |
paul@29 | 199 | #define INTIPCBASE 24 |
paul@29 | 200 | |
paul@14 | 201 | /* Output compare conveniences. */ |
paul@14 | 202 | |
paul@21 | 203 | #define OC1CON 0xBF803000 |
paul@21 | 204 | #define OC2CON 0xBF803200 |
paul@21 | 205 | #define OC3CON 0xBF803400 |
paul@21 | 206 | #define OC4CON 0xBF803600 |
paul@21 | 207 | #define OC5CON 0xBF803800 |
paul@14 | 208 | |
paul@21 | 209 | #define OCMIN 1 |
paul@21 | 210 | #define OCMAX 5 |
paul@21 | 211 | #define OCBASE OC1CON |
paul@21 | 212 | #define OCSTEP (OC2CON - OC1CON) |
paul@14 | 213 | |
paul@21 | 214 | #define OCxCON 0x00 |
paul@21 | 215 | #define OCxR 0x10 |
paul@21 | 216 | #define OCxRS 0x20 |
paul@14 | 217 | |
paul@21 | 218 | #define OCIEC IEC0 |
paul@14 | 219 | |
paul@21 | 220 | #define OCxIE 1 |
paul@14 | 221 | |
paul@21 | 222 | #define OCIFS IFS0 |
paul@14 | 223 | |
paul@21 | 224 | #define OCxIF 1 |
paul@14 | 225 | |
paul@21 | 226 | #define OCINTBASE 7 |
paul@21 | 227 | #define OCINTSTEP 5 |
paul@14 | 228 | |
paul@21 | 229 | #define OC1IPC IPC1 |
paul@21 | 230 | #define OC2IPC IPC2 |
paul@21 | 231 | #define OC3IPC IPC3 |
paul@21 | 232 | #define OC4IPC IPC4 |
paul@21 | 233 | #define OC5IPC IPC5 |
paul@21 | 234 | #define OCIPCBASE 16 |
paul@14 | 235 | |
paul@32 | 236 | /* Parallel mode conveniences. */ |
paul@32 | 237 | |
paul@32 | 238 | #define PMCON 0xBF807000 |
paul@32 | 239 | |
paul@32 | 240 | #define PMxCON 0x00 |
paul@32 | 241 | #define PMxMODE 0x10 |
paul@32 | 242 | #define PMxADDR 0x20 |
paul@32 | 243 | #define PMxDOUT 0x30 |
paul@32 | 244 | #define PMxDIN 0x40 |
paul@32 | 245 | #define PMxAEN 0x50 |
paul@32 | 246 | #define PMxSTAT 0x60 |
paul@32 | 247 | |
paul@32 | 248 | #define PMMIN 0 |
paul@32 | 249 | #define PMMAX 0 |
paul@32 | 250 | #define PMBASE PMCON |
paul@32 | 251 | #define PMSTEP 0 |
paul@32 | 252 | |
paul@32 | 253 | #define PMIEC IEC1 |
paul@32 | 254 | |
paul@32 | 255 | #define PMxIE 1 |
paul@32 | 256 | #define PMxEIE 2 |
paul@32 | 257 | |
paul@32 | 258 | #define PMIFS IFS1 |
paul@32 | 259 | |
paul@32 | 260 | #define PMxIF 1 |
paul@32 | 261 | #define PMxEIF 2 |
paul@32 | 262 | |
paul@32 | 263 | #define PMINTBASE 16 |
paul@32 | 264 | #define PMINTSTEP 0 |
paul@32 | 265 | |
paul@32 | 266 | #define PMIPC IPC8 |
paul@32 | 267 | #define PMIPCBASE 24 |
paul@32 | 268 | |
paul@7 | 269 | /* Timer conveniences. */ |
paul@7 | 270 | |
paul@21 | 271 | #define T1CON 0xBF800600 |
paul@21 | 272 | #define T2CON 0xBF800800 |
paul@21 | 273 | #define T3CON 0xBF800A00 |
paul@21 | 274 | #define T4CON 0xBF800C00 |
paul@21 | 275 | #define T5CON 0xBF800E00 |
paul@7 | 276 | |
paul@21 | 277 | #define TIMERMIN 1 |
paul@21 | 278 | #define TIMERMAX 5 |
paul@21 | 279 | #define TIMERBASE T1CON |
paul@21 | 280 | #define TIMERSTEP (T2CON - T1CON) |
paul@7 | 281 | |
paul@21 | 282 | #define TxCON 0x00 |
paul@21 | 283 | #define TMRx 0x10 |
paul@21 | 284 | #define PRx 0x20 |
paul@7 | 285 | |
paul@21 | 286 | #define TIMERIEC IEC0 |
paul@7 | 287 | |
paul@21 | 288 | #define TxIE 1 |
paul@7 | 289 | |
paul@85 | 290 | #define TIMERIFS IFS0 |
paul@7 | 291 | |
paul@21 | 292 | #define TxIF 1 |
paul@7 | 293 | |
paul@21 | 294 | #define TIMERINTBASE 4 |
paul@21 | 295 | #define TIMERINTSTEP 5 |
paul@7 | 296 | |
paul@21 | 297 | #define TIMER1IPC IPC1 |
paul@21 | 298 | #define TIMER2IPC IPC2 |
paul@21 | 299 | #define TIMER3IPC IPC3 |
paul@21 | 300 | #define TIMER4IPC IPC4 |
paul@21 | 301 | #define TIMER5IPC IPC5 |
paul@21 | 302 | #define TIMERIPCBASE 0 |
paul@7 | 303 | |
paul@58 | 304 | #define TIMERINTNUMBASE 4 |
paul@58 | 305 | #define TIMERINTNUMSTEP 5 |
paul@58 | 306 | |
paul@3 | 307 | /* UART conveniences. */ |
paul@3 | 308 | |
paul@21 | 309 | #define U1MODE 0xBF806000 |
paul@21 | 310 | #define U2MODE 0xBF806200 |
paul@3 | 311 | |
paul@21 | 312 | #define UARTMIN 1 |
paul@21 | 313 | #define UARTMAX 2 |
paul@21 | 314 | #define UARTBASE U1MODE |
paul@21 | 315 | #define UARTSTEP (U2MODE - U1MODE) |
paul@3 | 316 | |
paul@21 | 317 | #define UxMODE 0x00 |
paul@21 | 318 | #define UxSTA 0x10 |
paul@21 | 319 | #define UxTXREG 0x20 |
paul@21 | 320 | #define UxRXREG 0x30 |
paul@21 | 321 | #define UxBRG 0x40 |
paul@3 | 322 | |
paul@21 | 323 | #define UARTIEC IEC1 |
paul@6 | 324 | |
paul@21 | 325 | #define UxEIE 1 |
paul@21 | 326 | #define UxRIE 2 |
paul@21 | 327 | #define UxTIE 4 |
paul@6 | 328 | |
paul@21 | 329 | #define UARTIFS IFS1 |
paul@6 | 330 | |
paul@21 | 331 | #define UxEIF 1 |
paul@21 | 332 | #define UxRIF 2 |
paul@21 | 333 | #define UxTIF 4 |
paul@6 | 334 | |
paul@21 | 335 | #define UARTINTBASE 7 |
paul@21 | 336 | #define UARTINTSTEP 14 |
paul@6 | 337 | |
paul@21 | 338 | #define UART1IPC IPC8 |
paul@21 | 339 | #define UART1IPCBASE 0 |
paul@21 | 340 | #define UART2IPC IPC9 |
paul@21 | 341 | #define UART2IPCBASE 8 |
paul@3 | 342 | |
paul@3 | 343 | /* Interrupt numbers. |
paul@3 | 344 | * See... |
paul@3 | 345 | * TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION |
paul@3 | 346 | * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet |
paul@3 | 347 | */ |
paul@3 | 348 | |
paul@21 | 349 | #define DMA0 60 |
paul@21 | 350 | #define DMA1 61 |
paul@21 | 351 | #define DMA2 62 |
paul@21 | 352 | #define DMA3 63 |
paul@29 | 353 | #define INT0 3 |
paul@29 | 354 | #define INT1 8 |
paul@29 | 355 | #define INT2 13 |
paul@29 | 356 | #define INT3 18 |
paul@29 | 357 | #define INT4 23 |
paul@21 | 358 | #define OC1 7 |
paul@21 | 359 | #define OC2 12 |
paul@21 | 360 | #define OC3 17 |
paul@21 | 361 | #define OC4 22 |
paul@21 | 362 | #define OC5 27 |
paul@32 | 363 | #define PMP 48 |
paul@32 | 364 | #define PMPE 49 |
paul@21 | 365 | #define T1 4 |
paul@21 | 366 | #define T2 9 |
paul@21 | 367 | #define T3 14 |
paul@21 | 368 | #define T4 19 |
paul@21 | 369 | #define T5 24 |
paul@21 | 370 | #define U1RX 40 |
paul@21 | 371 | #define U1TX 41 |
paul@21 | 372 | #define U2RX 54 |
paul@21 | 373 | #define U2TX 55 |
paul@3 | 374 | |
paul@3 | 375 | /* Address modifiers. |
paul@3 | 376 | * See... |
paul@3 | 377 | * 11.2 CLR, SET and INV Registers |
paul@3 | 378 | * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet |
paul@3 | 379 | */ |
paul@3 | 380 | |
paul@21 | 381 | #define CLR 0x4 |
paul@21 | 382 | #define SET 0x8 |
paul@21 | 383 | #define INV 0xC |
paul@0 | 384 | |
paul@0 | 385 | #endif /* __PIC32_H__ */ |