paul@0 | 1 | #ifndef __PIC32_H__ |
paul@0 | 2 | #define __PIC32_H__ |
paul@0 | 3 | |
paul@3 | 4 | /* Peripheral addresses. |
paul@3 | 5 | * See... |
paul@0 | 6 | * TABLE 4-1: SFR MEMORYMAP |
paul@0 | 7 | * TABLE 11-3: PORTA REGISTER MAP |
paul@0 | 8 | * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet |
paul@0 | 9 | */ |
paul@0 | 10 | |
paul@0 | 11 | #define OC1CON 0xBF803000 |
paul@0 | 12 | #define OC1R 0xBF803010 |
paul@0 | 13 | #define OC1RS 0xBF803020 |
paul@0 | 14 | #define OC2CON 0xBF803200 |
paul@0 | 15 | #define OC2R 0xBF803210 |
paul@0 | 16 | #define OC2RS 0xBF803220 |
paul@0 | 17 | #define OC3CON 0xBF803400 |
paul@0 | 18 | #define OC3R 0xBF803410 |
paul@0 | 19 | #define OC3RS 0xBF803420 |
paul@0 | 20 | |
paul@0 | 21 | #define PMCON 0xBF807000 |
paul@0 | 22 | #define PMMODE 0xBF807010 |
paul@0 | 23 | #define PMADDR 0xBF807020 |
paul@0 | 24 | #define PMDOUT 0xBF807030 |
paul@0 | 25 | #define PMDIN 0xBF807040 |
paul@0 | 26 | #define PMAEN 0xBF807050 |
paul@0 | 27 | #define PMSTAT 0xBF807060 |
paul@0 | 28 | |
paul@0 | 29 | #define OSCCON 0xBF80F000 |
paul@0 | 30 | #define REFOCON 0xBF80F020 |
paul@0 | 31 | #define REFOTRIM 0xBF80F030 |
paul@0 | 32 | #define CFGCON 0xBF80F200 |
paul@0 | 33 | #define SYSKEY 0xBF80F230 |
paul@0 | 34 | |
paul@0 | 35 | #define U1RXR 0xBF80FA50 |
paul@0 | 36 | |
paul@0 | 37 | #define RPA0R 0xBF80FB00 |
paul@0 | 38 | #define RPA1R 0xBF80FB04 |
paul@0 | 39 | #define RPA2R 0xBF80FB08 |
paul@0 | 40 | #define RPA3R 0xBF80FB0C |
paul@0 | 41 | #define RPA4R 0xBF80FB10 |
paul@0 | 42 | #define RPB0R 0xBF80FB2C |
paul@0 | 43 | #define RPB1R 0xBF80FB30 |
paul@0 | 44 | #define RPB2R 0xBF80FB34 |
paul@0 | 45 | #define RPB3R 0xBF80FB38 |
paul@0 | 46 | #define RPB4R 0xBF80FB3C |
paul@0 | 47 | #define RPB5R 0xBF80FB40 |
paul@0 | 48 | #define RPB10R 0xBF80FB54 |
paul@0 | 49 | #define RPB15R 0xBF80FB68 |
paul@0 | 50 | |
paul@0 | 51 | #define INTCON 0xBF881000 |
paul@0 | 52 | #define IFS0 0xBF881030 |
paul@0 | 53 | #define IFS1 0xBF881040 |
paul@0 | 54 | #define IEC0 0xBF881060 |
paul@0 | 55 | #define IEC1 0xBF881070 |
paul@0 | 56 | #define IPC1 0xBF8810A0 |
paul@0 | 57 | #define IPC2 0xBF8810B0 |
paul@3 | 58 | #define IPC3 0xBF8810C0 |
paul@3 | 59 | #define IPC4 0xBF8810D0 |
paul@3 | 60 | #define IPC5 0xBF8810E0 |
paul@3 | 61 | #define IPC6 0xBF8810F0 |
paul@0 | 62 | #define IPC7 0xBF881100 |
paul@0 | 63 | #define IPC8 0xBF881110 |
paul@3 | 64 | #define IPC9 0xBF881120 |
paul@0 | 65 | #define IPC10 0xBF881130 |
paul@0 | 66 | |
paul@0 | 67 | #define BMXCON 0xBF882000 |
paul@0 | 68 | #define BMXDKPBA 0xBF882010 |
paul@0 | 69 | #define BMXDUDBA 0xBF882020 |
paul@0 | 70 | #define BMXDUPBA 0xBF882030 |
paul@0 | 71 | #define BMXDRMSZ 0xBF882040 |
paul@0 | 72 | |
paul@0 | 73 | #define ANSELA 0xBF886000 |
paul@0 | 74 | #define TRISA 0xBF886010 |
paul@0 | 75 | #define PORTA 0xBF886020 |
paul@0 | 76 | #define LATA 0xBF886030 |
paul@0 | 77 | #define ODCA 0xBF886040 |
paul@0 | 78 | #define ANSELB 0xBF886100 |
paul@0 | 79 | #define TRISB 0xBF886110 |
paul@0 | 80 | #define PORTB 0xBF886120 |
paul@0 | 81 | #define LATB 0xBF886130 |
paul@0 | 82 | #define ODCB 0xBF886140 |
paul@0 | 83 | |
paul@3 | 84 | /* DMA conveniences. */ |
paul@3 | 85 | |
paul@3 | 86 | #define DMACON 0xBF883000 |
paul@3 | 87 | #define DCH0CON 0xBF883060 |
paul@3 | 88 | #define DCH1CON 0xBF883120 |
paul@3 | 89 | #define DCH2CON 0xBF8831E0 |
paul@3 | 90 | #define DCH3CON 0xBF8832A0 |
paul@3 | 91 | |
paul@3 | 92 | #define DCHMIN 0 |
paul@3 | 93 | #define DCHMAX 3 |
paul@3 | 94 | #define DCHBASE DCH0CON |
paul@3 | 95 | #define DCHSTEP (DCH1CON - DCH0CON) |
paul@3 | 96 | |
paul@3 | 97 | #define DCHxCON 0x00 |
paul@3 | 98 | #define DCHxECON 0x10 |
paul@3 | 99 | #define DCHxINT 0x20 |
paul@3 | 100 | #define DCHxSSA 0x30 |
paul@3 | 101 | #define DCHxDSA 0x40 |
paul@3 | 102 | #define DCHxSSIZ 0x50 |
paul@9 | 103 | #define DCHxDSIZ 0x60 |
paul@9 | 104 | #define DCHxSPTR 0x70 |
paul@9 | 105 | #define DCHxDPTR 0x80 |
paul@3 | 106 | #define DCHxCSIZ 0x90 |
paul@9 | 107 | #define DCHxCPTR 0xA0 |
paul@9 | 108 | #define DCHxDAT 0xB0 |
paul@3 | 109 | |
paul@3 | 110 | #define DMAIEC IEC1 |
paul@3 | 111 | #define DMAIFS IFS1 |
paul@3 | 112 | #define DMAINTBASE 28 |
paul@3 | 113 | #define DMAIPC IPC10 |
paul@3 | 114 | #define DCHIPCBASE 0 |
paul@3 | 115 | #define DCHIPCSTEP 8 |
paul@3 | 116 | |
paul@7 | 117 | /* Timer conveniences. */ |
paul@7 | 118 | |
paul@7 | 119 | #define T1CON 0xBF800600 |
paul@7 | 120 | #define T2CON 0xBF800800 |
paul@7 | 121 | #define T3CON 0xBF800A00 |
paul@7 | 122 | #define T4CON 0xBF800C00 |
paul@7 | 123 | #define T5CON 0xBF800E00 |
paul@7 | 124 | |
paul@7 | 125 | #define TIMERMIN 1 |
paul@7 | 126 | #define TIMERMAX 5 |
paul@7 | 127 | #define TIMERBASE T1CON |
paul@7 | 128 | #define TIMERSTEP (T2CON - T1CON) |
paul@7 | 129 | |
paul@7 | 130 | #define TxCON 0x00 |
paul@7 | 131 | #define TMRx 0x10 |
paul@7 | 132 | #define PRx 0x20 |
paul@7 | 133 | |
paul@7 | 134 | #define TIMERIEC IEC0 |
paul@7 | 135 | |
paul@7 | 136 | #define TxIE 1 |
paul@7 | 137 | |
paul@7 | 138 | #define TIMERIFS IEC0 |
paul@7 | 139 | |
paul@7 | 140 | #define TxIF 1 |
paul@7 | 141 | |
paul@7 | 142 | #define TIMERINTBASE 4 |
paul@7 | 143 | #define TIMERINTSTEP 5 |
paul@7 | 144 | |
paul@7 | 145 | #define TIMER1IPC IPC1 |
paul@7 | 146 | #define TIMER2IPC IPC2 |
paul@7 | 147 | #define TIMER3IPC IPC3 |
paul@7 | 148 | #define TIMER4IPC IPC4 |
paul@7 | 149 | #define TIMER5IPC IPC5 |
paul@7 | 150 | #define TIMERIPCBASE 0 |
paul@7 | 151 | |
paul@3 | 152 | /* UART conveniences. */ |
paul@3 | 153 | |
paul@3 | 154 | #define U1MODE 0xBF806000 |
paul@3 | 155 | #define U2MODE 0xBF806200 |
paul@3 | 156 | |
paul@3 | 157 | #define UARTMIN 1 |
paul@3 | 158 | #define UARTMAX 2 |
paul@3 | 159 | #define UARTBASE U1MODE |
paul@3 | 160 | #define UARTSTEP (U2MODE - U1MODE) |
paul@3 | 161 | |
paul@3 | 162 | #define UxMODE 0x00 |
paul@3 | 163 | #define UxSTA 0x10 |
paul@3 | 164 | #define UxTXREG 0x20 |
paul@3 | 165 | #define UxRXREG 0x30 |
paul@3 | 166 | #define UxBRG 0x40 |
paul@3 | 167 | |
paul@3 | 168 | #define UARTIEC IEC1 |
paul@6 | 169 | |
paul@6 | 170 | #define UxEIE 1 |
paul@6 | 171 | #define UxRIE 2 |
paul@6 | 172 | #define UxTIE 4 |
paul@6 | 173 | |
paul@3 | 174 | #define UARTIFS IFS1 |
paul@6 | 175 | |
paul@6 | 176 | #define UxEIF 1 |
paul@6 | 177 | #define UxRIF 2 |
paul@6 | 178 | #define UxTIF 4 |
paul@6 | 179 | |
paul@3 | 180 | #define UARTINTBASE 7 |
paul@3 | 181 | #define UARTINTSTEP 14 |
paul@6 | 182 | |
paul@3 | 183 | #define UART1IPC IPC8 |
paul@3 | 184 | #define UART1IPCBASE 0 |
paul@3 | 185 | #define UART2IPC IPC9 |
paul@3 | 186 | #define UART2IPCBASE 8 |
paul@3 | 187 | |
paul@3 | 188 | /* Interrupt numbers. |
paul@3 | 189 | * See... |
paul@3 | 190 | * TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION |
paul@3 | 191 | * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet |
paul@3 | 192 | */ |
paul@3 | 193 | |
paul@9 | 194 | #define DMA0 60 |
paul@9 | 195 | #define DMA1 61 |
paul@9 | 196 | #define DMA2 62 |
paul@9 | 197 | #define DMA3 63 |
paul@7 | 198 | #define T1 4 |
paul@7 | 199 | #define T2 9 |
paul@7 | 200 | #define T3 14 |
paul@7 | 201 | #define T4 19 |
paul@7 | 202 | #define T5 24 |
paul@3 | 203 | #define U1RX 40 |
paul@9 | 204 | #define U1TX 41 |
paul@3 | 205 | #define U2RX 54 |
paul@9 | 206 | #define U2TX 55 |
paul@3 | 207 | |
paul@3 | 208 | /* Address modifiers. |
paul@3 | 209 | * See... |
paul@3 | 210 | * 11.2 CLR, SET and INV Registers |
paul@3 | 211 | * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet |
paul@3 | 212 | */ |
paul@3 | 213 | |
paul@3 | 214 | #define CLR 0x4 |
paul@3 | 215 | #define SET 0x8 |
paul@3 | 216 | #define INV 0xC |
paul@0 | 217 | |
paul@0 | 218 | #endif /* __PIC32_H__ */ |