paul@15 | 1 | /* |
paul@15 | 2 | * A demonstration of various PIC32 peripherals. |
paul@15 | 3 | * |
paul@16 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@15 | 5 | * |
paul@15 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@15 | 7 | * it under the terms of the GNU General Public License as published by |
paul@15 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@15 | 9 | * (at your option) any later version. |
paul@15 | 10 | * |
paul@15 | 11 | * This program is distributed in the hope that it will be useful, |
paul@15 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@15 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@15 | 14 | * GNU General Public License for more details. |
paul@15 | 15 | * |
paul@15 | 16 | * You should have received a copy of the GNU General Public License |
paul@15 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@15 | 18 | */ |
paul@15 | 19 | |
paul@15 | 20 | |
paul@0 | 21 | #include "pic32_c.h" |
paul@0 | 22 | #include "init.h" |
paul@11 | 23 | #include "debug.h" |
paul@47 | 24 | |
paul@47 | 25 | /* Specific functionality. */ |
paul@47 | 26 | |
paul@16 | 27 | #include "main.h" |
paul@47 | 28 | #include "devconfig.h" |
paul@0 | 29 | |
paul@13 | 30 | static const char message1[] = "Hello!\r\n"; |
paul@44 | 31 | |
paul@44 | 32 | #define CELLSIZE4 |
paul@44 | 33 | |
paul@44 | 34 | #ifdef CELLSIZE1 |
paul@44 | 35 | static const char message2[] = "Adoc gi,hlo\r"; |
paul@44 | 36 | static const char message3[] = "n neaan el!\n"; |
paul@44 | 37 | #define CELLSIZE 1 |
paul@44 | 38 | #endif |
paul@44 | 39 | |
paul@44 | 40 | #ifdef CELLSIZE4 |
paul@44 | 41 | static const char message2[] = "And agahell"; |
paul@44 | 42 | static const char message3[] = "oncein, o!\r\n"; |
paul@44 | 43 | #define CELLSIZE 4 |
paul@44 | 44 | #endif |
paul@44 | 45 | |
paul@24 | 46 | static int uart_echo; |
paul@0 | 47 | |
paul@15 | 48 | |
paul@15 | 49 | |
paul@16 | 50 | /* Blink an attached LED with delays implemented using a loop. */ |
paul@16 | 51 | |
paul@0 | 52 | static void blink(uint32_t delay, uint32_t port, uint32_t pins) |
paul@0 | 53 | { |
paul@0 | 54 | uint32_t counter; |
paul@0 | 55 | |
paul@0 | 56 | /* Clear outputs (LED). */ |
paul@0 | 57 | |
paul@0 | 58 | CLR_REG(port, pins); |
paul@0 | 59 | |
paul@0 | 60 | while (1) |
paul@0 | 61 | { |
paul@0 | 62 | counter = delay; |
paul@0 | 63 | |
paul@0 | 64 | while (counter--) __asm__(""); /* retain loop */ |
paul@0 | 65 | |
paul@0 | 66 | /* Invert outputs (LED). */ |
paul@0 | 67 | |
paul@0 | 68 | INV_REG(port, pins); |
paul@0 | 69 | } |
paul@0 | 70 | } |
paul@0 | 71 | |
paul@16 | 72 | |
paul@16 | 73 | |
paul@16 | 74 | /* Main program. */ |
paul@16 | 75 | |
paul@0 | 76 | void main(void) |
paul@0 | 77 | { |
paul@24 | 78 | uart_echo = 0; |
paul@24 | 79 | |
paul@0 | 80 | init_memory(); |
paul@0 | 81 | init_pins(); |
paul@0 | 82 | init_outputs(); |
paul@0 | 83 | |
paul@0 | 84 | unlock_config(); |
paul@0 | 85 | config_uart(); |
paul@0 | 86 | lock_config(); |
paul@0 | 87 | |
paul@11 | 88 | init_dma(); |
paul@3 | 89 | |
paul@26 | 90 | /* Peripheral relationships: |
paul@26 | 91 | |
paul@44 | 92 | Timer3 -> OC1 -> DMA0: message2 -> U1TXREG |
paul@44 | 93 | ___/ |
paul@44 | 94 | / |
paul@44 | 95 | Timer2 -> DMA1: message1 -> U1TXREG |
paul@26 | 96 | \___ |
paul@26 | 97 | \ |
paul@44 | 98 | Timer3 -> OC1 -> DMA2: message3 -> U1TXREG |
paul@26 | 99 | */ |
paul@26 | 100 | |
paul@44 | 101 | /* Enable DMA on the next channel's completion, with OC1 initiating |
paul@44 | 102 | transfers, raising a transfer completion interrupt to be handled. */ |
paul@44 | 103 | |
paul@44 | 104 | dma_init(0, 2); |
paul@44 | 105 | dma_set_chaining(0, dma_chain_next); |
paul@44 | 106 | dma_set_interrupt(0, OC1, 1); |
paul@44 | 107 | dma_set_transfer(0, PHYSICAL((uint32_t) message2), sizeof(message2) - 1, |
paul@44 | 108 | HW_PHYSICAL(UART_REG(1, UxTXREG)), 1, |
paul@44 | 109 | CELLSIZE); |
paul@44 | 110 | |
paul@13 | 111 | /* Initiate DMA on the Timer2 interrupt. Since the channel is not |
paul@20 | 112 | auto-enabled, it must be explicitly enabled elsewhere (when a UART |
paul@20 | 113 | interrupt is handled). */ |
paul@11 | 114 | |
paul@44 | 115 | dma_init(1, 3); |
paul@44 | 116 | dma_set_interrupt(1, T2, 1); |
paul@44 | 117 | dma_set_transfer(1, PHYSICAL((uint32_t) message1), sizeof(message1) - 1, |
paul@13 | 118 | HW_PHYSICAL(UART_REG(1, UxTXREG)), 1, |
paul@13 | 119 | 1); |
paul@13 | 120 | |
paul@14 | 121 | /* Enable DMA on the preceding channel's completion, with OC1 initiating |
paul@14 | 122 | transfers, raising a transfer completion interrupt to be handled. */ |
paul@13 | 123 | |
paul@44 | 124 | dma_init(2, 2); |
paul@44 | 125 | dma_set_chaining(2, dma_chain_previous); |
paul@44 | 126 | dma_set_interrupt(2, OC1, 1); |
paul@44 | 127 | dma_set_transfer(2, PHYSICAL((uint32_t) message3), sizeof(message3) - 1, |
paul@3 | 128 | HW_PHYSICAL(UART_REG(1, UxTXREG)), 1, |
paul@44 | 129 | CELLSIZE); |
paul@44 | 130 | dma_init_interrupt(2, 0b00001000, 7, 3); |
paul@13 | 131 | |
paul@14 | 132 | /* Configure a timer for the first DMA channel whose interrupt condition |
paul@26 | 133 | drives the transfer. The interrupt itself does not need to be enabled. */ |
paul@3 | 134 | |
paul@13 | 135 | timer_init(2, 0b111, 60000); |
paul@13 | 136 | timer_on(2); |
paul@13 | 137 | |
paul@14 | 138 | /* Configure a timer for the output compare unit below. */ |
paul@14 | 139 | |
paul@14 | 140 | timer_init(3, 0b111, 20000); |
paul@13 | 141 | timer_on(3); |
paul@13 | 142 | |
paul@14 | 143 | /* Configure output compare in dual compare (continuous output) mode using |
paul@14 | 144 | Timer3 as time base. The interrupt condition drives the second DMA |
paul@26 | 145 | channel but does not need to be enabled. */ |
paul@14 | 146 | |
paul@14 | 147 | oc_init(1, 0b101, 3); |
paul@14 | 148 | oc_set_pulse(1, 10000); |
paul@14 | 149 | oc_set_pulse_end(1, 20000); |
paul@14 | 150 | oc_on(1); |
paul@14 | 151 | |
paul@20 | 152 | /* Set UART interrupt priority above CPU priority to process events and to |
paul@20 | 153 | enable the first DMA channel. */ |
paul@3 | 154 | |
paul@47 | 155 | uart_init(1, FPB, 115200); |
paul@13 | 156 | uart_init_interrupt(1, UxRIF, 7, 3); |
paul@3 | 157 | uart_on(1); |
paul@0 | 158 | |
paul@0 | 159 | interrupts_on(); |
paul@0 | 160 | |
paul@0 | 161 | blink(3 << 24, PORTA, 1 << 3); |
paul@0 | 162 | } |
paul@0 | 163 | |
paul@16 | 164 | |
paul@16 | 165 | |
paul@16 | 166 | /* Exception and interrupt handlers. */ |
paul@16 | 167 | |
paul@0 | 168 | void exception_handler(void) |
paul@0 | 169 | { |
paul@0 | 170 | blink(3 << 12, PORTA, 1 << 3); |
paul@0 | 171 | } |
paul@0 | 172 | |
paul@0 | 173 | void interrupt_handler(void) |
paul@0 | 174 | { |
paul@19 | 175 | uint32_t ifs; |
paul@19 | 176 | char val; |
paul@11 | 177 | |
paul@3 | 178 | /* Check for a UART receive interrupt condition (UxRIF). */ |
paul@0 | 179 | |
paul@11 | 180 | ifs = REG(UARTIFS) & UART_INT_FLAGS(1, UxRIF); |
paul@8 | 181 | |
paul@8 | 182 | if (ifs) |
paul@3 | 183 | { |
paul@8 | 184 | /* Clear the UART interrupt condition. */ |
paul@8 | 185 | |
paul@8 | 186 | CLR_REG(UARTIFS, ifs); |
paul@8 | 187 | |
paul@3 | 188 | /* Write the received data back. */ |
paul@0 | 189 | |
paul@19 | 190 | while (uart_can_read(1)) |
paul@11 | 191 | { |
paul@19 | 192 | val = uart_read_char(1); |
paul@11 | 193 | if (uart_echo) |
paul@19 | 194 | uart_write_char(1, val); |
paul@13 | 195 | |
paul@13 | 196 | /* Initiate transfer upon receiving a particular character. */ |
paul@13 | 197 | |
paul@13 | 198 | if (val == '0') |
paul@44 | 199 | dma_on(1); |
paul@11 | 200 | } |
paul@11 | 201 | } |
paul@18 | 202 | |
paul@18 | 203 | /* Check for a DMA interrupt condition (CHBCIF). */ |
paul@18 | 204 | |
paul@44 | 205 | ifs = REG(DMAIFS) & DMA_INT_FLAGS(2, DCHxIF); |
paul@18 | 206 | |
paul@18 | 207 | if (ifs) |
paul@18 | 208 | { |
paul@18 | 209 | uart_write_string("CHBCIF\r\n"); |
paul@18 | 210 | INV_REG(PORTA, 1 << 2); |
paul@44 | 211 | CLR_REG(DMA_REG(2, DCHxINT), 0b11111111); |
paul@18 | 212 | CLR_REG(DMAIFS, ifs); |
paul@18 | 213 | } |
paul@0 | 214 | } |
paul@16 | 215 | |
paul@16 | 216 | |
paul@16 | 217 | |
paul@16 | 218 | /* Peripheral pin configuration. */ |
paul@16 | 219 | |
paul@16 | 220 | void config_uart(void) |
paul@16 | 221 | { |
paul@16 | 222 | /* Map U1RX to RPB13. */ |
paul@16 | 223 | |
paul@16 | 224 | REG(U1RXR) = 0b0011; /* U1RXR<3:0> = 0011 (RPB13) */ |
paul@16 | 225 | |
paul@16 | 226 | /* Map U1TX to RPB15. */ |
paul@16 | 227 | |
paul@16 | 228 | REG(RPB15R) = 0b0001; /* RPB15R<3:0> = 0001 (U1TX) */ |
paul@16 | 229 | |
paul@16 | 230 | /* Set RPB13 to input. */ |
paul@16 | 231 | |
paul@16 | 232 | SET_REG(TRISB, 1 << 13); |
paul@16 | 233 | } |