paul@87 | 1 | Introduction
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paul@87 | 2 | ------------
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paul@87 | 3 |
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paul@87 | 4 | This example demonstrates the generation of an analogue VGA signal from a
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paul@87 | 5 | PIC32 microcontroller using general output pins. Instead of using DMA, which
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paul@87 | 6 | was the focus of the VGAPIC32 project and is a central feature of the
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paul@87 | 7 | approaches demonstrated by other examples (vga, vga-dual, vga-pmp, vga-timer),
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paul@87 | 8 | here the CPU is given the task of transferring pixel data to the output pins.
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paul@87 | 9 |
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paul@87 | 10 | Instead of a timer interrupt condition initiating DMA transfers, the interrupt
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paul@87 | 11 | is handled and a routine invoked to issue the necessary load and store
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paul@87 | 12 | instructions in a loop. Otherwise, the use of the timer to generate sync
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paul@87 | 13 | pulses is as in the other examples and the general display state machine is
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paul@87 | 14 | largely the same.
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paul@87 | 15 |
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paul@87 | 16 | The resulting picture is more pleasing than that produced by most of the DMA
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paul@87 | 17 | examples in that the display pixels have consistent widths. Moreover, the
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paul@87 | 18 | pixels are also narrower than those produced by the vga-timer example. It is
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paul@87 | 19 | possible to generate a display with something approaching 200 pixels
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paul@87 | 20 | horizontally, with 160 pixels being demonstrated.
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paul@87 | 21 |
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paul@87 | 22 | However, the CPU now spends a lot of time occupied in an interrupt request
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paul@87 | 23 | handler generating pixels. This seems less elegant than using DMA, but in
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paul@87 | 24 | practice, the CPU may be effectively stalled where DMA transfers dominate
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paul@87 | 25 | access to the RAM. Even if, in such situations, the CPU may be able to access
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paul@87 | 26 | flash memory to load instructions, programs typically end up accessing RAM at
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paul@87 | 27 | some point, and this would effectively limit the concurrency within the
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paul@88 | 28 | system. Certainly, this approach seems to result in slower programs than the
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paul@88 | 29 | plain DMA-based approach.
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paul@87 | 30 |
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paul@87 | 31 | One potential advantage of this approach is in the flexibility that might be
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paul@87 | 32 | achieved by manipulating the pixel data. With DMA, data is transferred as it
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paul@87 | 33 | is found and is generally not transformed (although there are some features in
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paul@87 | 34 | the PIC32 DMA controller for certain kinds of data), whereas we might envisage
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paul@87 | 35 | supporting display modes employing fewer bits for the output signal, reducing
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paul@87 | 36 | the number of colours but also the size of the framebuffer.
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paul@87 | 37 |
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paul@87 | 38 | Hardware Details
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paul@87 | 39 | ================
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paul@87 | 40 |
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paul@87 | 41 | The pin usage of this solution is documented below.
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paul@87 | 42 |
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paul@87 | 43 | PIC32MX270F256B-50I/SP Pin Assignments
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paul@87 | 44 | --------------------------------------
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paul@87 | 45 |
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paul@87 | 46 | MCLR# 1 \/ 28
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paul@87 | 47 | HSYNC/OC1/RA0 2 27
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paul@87 | 48 | VSYNC/OC2/RA1 3 26 RB15/U1TX
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paul@87 | 49 | D0/RB0 4 25 RB14
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paul@87 | 50 | D1/RB1 5 24 RB13/U1RX
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paul@87 | 51 | D2/RB2 6 23
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paul@87 | 52 | D3/RB3 7 22 RB11/PGEC2
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paul@87 | 53 | 8 21 RB10/PGEC3
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paul@87 | 54 | RA2 9 20
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paul@87 | 55 | RA3 10 19
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paul@87 | 56 | D4/RB4 11 18 RB9
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paul@87 | 57 | 12 17 RB8
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paul@87 | 58 | 13 16 RB7/D7
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paul@87 | 59 | D5/RB5 14 15
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paul@87 | 60 |
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paul@87 | 61 | Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
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paul@87 | 62 | unlike the MX170 variant).
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paul@87 | 63 |
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paul@87 | 64 | UART Connections
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paul@87 | 65 | ----------------
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paul@87 | 66 |
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paul@87 | 67 | UART1 is exposed by the RB13 and RB15 pins.
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paul@87 | 68 |
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paul@87 | 69 | Data Signal Routing
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paul@87 | 70 | -------------------
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paul@87 | 71 |
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paul@87 | 72 | For one bit of intensity, two bits per colour channel:
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paul@87 | 73 |
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paul@87 | 74 | D7 -> 2200R -> I
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paul@87 | 75 |
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paul@87 | 76 | I -> diode -> R
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paul@87 | 77 | I -> diode -> G
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paul@87 | 78 | I -> diode -> B
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paul@87 | 79 |
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paul@87 | 80 | D6 (not connected)
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paul@87 | 81 |
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paul@87 | 82 | D5 -> 470R -> R
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paul@87 | 83 | D4 -> 1000R -> R
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paul@87 | 84 | D3 -> 470R -> G
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paul@87 | 85 | D2 -> 1000R -> G
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paul@87 | 86 | D1 -> 470R -> B
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paul@87 | 87 | D0 -> 1000R -> B
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paul@87 | 88 |
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paul@87 | 89 | HSYNC -> HS
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paul@87 | 90 | VSYNC -> VS
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paul@87 | 91 |
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paul@87 | 92 | Output Socket Pinout
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paul@87 | 93 | --------------------
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paul@87 | 94 |
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paul@87 | 95 | 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
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paul@87 | 96 |
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paul@87 | 97 | 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
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paul@87 | 98 |
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paul@87 | 99 | 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
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paul@87 | 100 |
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paul@87 | 101 | Output Cable Pinout
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paul@87 | 102 | -------------------
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paul@87 | 103 |
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paul@87 | 104 | 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
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paul@87 | 105 |
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paul@87 | 106 | 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
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paul@87 | 107 |
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paul@87 | 108 | 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
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paul@87 | 109 |
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paul@87 | 110 | References
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paul@87 | 111 | ----------
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paul@87 | 112 |
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paul@87 | 113 | https://en.wikipedia.org/wiki/VGA_connector
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paul@87 | 114 |
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paul@87 | 115 | http://papilio.cc/index.php?n=Papilio.VGAWing
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paul@87 | 116 |
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paul@87 | 117 | http://lucidscience.com/pro-vga%20video%20generator-2.aspx
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paul@87 | 118 |
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paul@87 | 119 | https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
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