paul@37 | 1 | /* |
paul@37 | 2 | * Generate a VGA signal using a PIC32 microcontroller. |
paul@37 | 3 | * |
paul@37 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@37 | 5 | * |
paul@37 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@37 | 7 | * it under the terms of the GNU General Public License as published by |
paul@37 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@37 | 9 | * (at your option) any later version. |
paul@37 | 10 | * |
paul@37 | 11 | * This program is distributed in the hope that it will be useful, |
paul@37 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@37 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@37 | 14 | * GNU General Public License for more details. |
paul@37 | 15 | * |
paul@37 | 16 | * You should have received a copy of the GNU General Public License |
paul@37 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@37 | 18 | */ |
paul@37 | 19 | |
paul@37 | 20 | |
paul@37 | 21 | #include "pic32_c.h" |
paul@37 | 22 | #include "init.h" |
paul@37 | 23 | #include "debug.h" |
paul@41 | 24 | |
paul@41 | 25 | /* Specific functionality. */ |
paul@41 | 26 | |
paul@37 | 27 | #include "main.h" |
paul@47 | 28 | #include "devconfig.h" |
paul@37 | 29 | #include "vga.h" |
paul@41 | 30 | #include "display.h" |
paul@49 | 31 | #include "display_config.h" |
paul@50 | 32 | #include "vga_display.h" |
paul@37 | 33 | |
paul@37 | 34 | |
paul@41 | 35 | |
paul@37 | 36 | /* Pixel data. */ |
paul@37 | 37 | |
paul@37 | 38 | static const uint8_t zerodata[ZERO_LENGTH] = {0}; |
paul@37 | 39 | |
paul@37 | 40 | |
paul@37 | 41 | |
paul@37 | 42 | /* Blink an attached LED with delays implemented using a loop. */ |
paul@37 | 43 | |
paul@37 | 44 | static void blink(uint32_t delay, uint32_t port, uint32_t pins) |
paul@37 | 45 | { |
paul@37 | 46 | uint32_t counter; |
paul@37 | 47 | |
paul@37 | 48 | /* Clear outputs (LED). */ |
paul@37 | 49 | |
paul@37 | 50 | CLR_REG(port, pins); |
paul@37 | 51 | |
paul@37 | 52 | while (1) |
paul@37 | 53 | { |
paul@37 | 54 | counter = delay; |
paul@37 | 55 | |
paul@37 | 56 | while (counter--) __asm__(""); /* retain loop */ |
paul@37 | 57 | |
paul@37 | 58 | /* Invert outputs (LED). */ |
paul@37 | 59 | |
paul@37 | 60 | INV_REG(port, pins); |
paul@37 | 61 | } |
paul@37 | 62 | } |
paul@37 | 63 | |
paul@37 | 64 | |
paul@37 | 65 | |
paul@37 | 66 | /* Main program. */ |
paul@37 | 67 | |
paul@37 | 68 | void main(void) |
paul@37 | 69 | { |
paul@50 | 70 | init_vga(&display_config, start_visible, update_visible, stop_visible, |
paul@50 | 71 | vsync_high, vsync_low); |
paul@50 | 72 | |
paul@49 | 73 | test_linedata(&display_config); |
paul@37 | 74 | |
paul@37 | 75 | init_memory(); |
paul@37 | 76 | init_pins(); |
paul@37 | 77 | init_outputs(); |
paul@37 | 78 | |
paul@37 | 79 | unlock_config(); |
paul@37 | 80 | config_oc(); |
paul@37 | 81 | config_uart(); |
paul@37 | 82 | lock_config(); |
paul@37 | 83 | |
paul@37 | 84 | init_dma(); |
paul@37 | 85 | |
paul@37 | 86 | /* Peripheral relationships: |
paul@37 | 87 | |
paul@37 | 88 | Timer2 -> OC1 |
paul@37 | 89 | -> OC2 (vertical sync region) |
paul@46 | 90 | -> DMA1: zerodata -> PORTB (visible region) |
paul@37 | 91 | | |
paul@46 | 92 | Timer3 -> DMA0: linedata -> PORTB |
paul@46 | 93 | Timer3 -> DMA2: linedata -> PORTB |
paul@37 | 94 | | |
paul@46 | 95 | Timer3 -> DMA3: zerodata -> PORTB |
paul@37 | 96 | */ |
paul@37 | 97 | |
paul@37 | 98 | /* Initiate DMA on the Timer2 interrupt condition, transferring line data to |
paul@37 | 99 | the first byte of PORTB. Do not enable the channel for initiation until |
paul@37 | 100 | the visible region is about to start. */ |
paul@37 | 101 | |
paul@46 | 102 | dma_init(1, 3); |
paul@46 | 103 | dma_set_auto_enable(1, 1); |
paul@46 | 104 | dma_set_interrupt(1, T2, 1); |
paul@46 | 105 | dma_set_transfer(1, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH, |
paul@37 | 106 | HW_PHYSICAL(PORTB), 1, |
paul@37 | 107 | ZERO_LENGTH); |
paul@37 | 108 | |
paul@46 | 109 | /* Enable DMA on the zero channel's completion, with the Timer3 |
paul@37 | 110 | interrupt condition initiating transfers. */ |
paul@37 | 111 | |
paul@46 | 112 | dma_init(0, 3); |
paul@46 | 113 | dma_set_chaining(0, dma_chain_next); |
paul@46 | 114 | dma_set_interrupt(0, T3, 1); |
paul@49 | 115 | dma_set_transfer(0, PHYSICAL((uint32_t) display_config.screen_start), |
paul@49 | 116 | display_config.line_length / 2, |
paul@37 | 117 | HW_PHYSICAL(PORTB), 1, |
paul@46 | 118 | TRANSFER_CELL_SIZE); |
paul@46 | 119 | |
paul@46 | 120 | /* Enable DMA on the zero channel's completion, with the Timer3 |
paul@46 | 121 | interrupt condition initiating transfers. */ |
paul@46 | 122 | |
paul@46 | 123 | dma_init(2, 3); |
paul@46 | 124 | dma_set_chaining(2, dma_chain_previous); |
paul@46 | 125 | dma_set_interrupt(2, T3, 1); |
paul@49 | 126 | dma_set_transfer(2, PHYSICAL((uint32_t) display_config.screen_start + |
paul@49 | 127 | display_config.line_length / 2), |
paul@49 | 128 | display_config.line_length / 2, |
paul@46 | 129 | HW_PHYSICAL(PORTB), 1, |
paul@46 | 130 | TRANSFER_CELL_SIZE); |
paul@37 | 131 | |
paul@37 | 132 | /* Enable DMA on the preceding channel's completion, with this also |
paul@37 | 133 | initiating transfers. */ |
paul@37 | 134 | |
paul@46 | 135 | dma_init(3, 3); |
paul@46 | 136 | dma_set_chaining(3, dma_chain_previous); |
paul@46 | 137 | dma_set_interrupt(3, T3, 1); |
paul@46 | 138 | dma_set_transfer(3, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH, |
paul@37 | 139 | HW_PHYSICAL(PORTB), 1, |
paul@37 | 140 | ZERO_LENGTH); |
paul@46 | 141 | dma_set_receive_events(3, 1); |
paul@37 | 142 | |
paul@37 | 143 | /* Configure a timer for the horizontal sync. The timer has no prescaling |
paul@37 | 144 | (0). */ |
paul@37 | 145 | |
paul@37 | 146 | timer_init(2, 0, HFREQ_LIMIT); |
paul@37 | 147 | timer_on(2); |
paul@37 | 148 | |
paul@37 | 149 | /* Configure a timer for line data transfers. */ |
paul@37 | 150 | |
paul@37 | 151 | timer_init(3, 0, 1); |
paul@37 | 152 | timer_on(3); |
paul@37 | 153 | |
paul@37 | 154 | /* Horizontal sync. */ |
paul@37 | 155 | |
paul@37 | 156 | /* Configure output compare in dual compare (continuous output) mode using |
paul@37 | 157 | Timer2 as time base. The interrupt condition drives the first DMA channel |
paul@37 | 158 | and is handled to drive the display state machine. */ |
paul@37 | 159 | |
paul@37 | 160 | oc_init(1, 0b101, 2); |
paul@37 | 161 | oc_set_pulse(1, HSYNC_END); |
paul@37 | 162 | oc_set_pulse_end(1, HSYNC_START); |
paul@37 | 163 | oc_init_interrupt(1, 7, 3); |
paul@37 | 164 | oc_on(1); |
paul@37 | 165 | |
paul@37 | 166 | /* Vertical sync. */ |
paul@37 | 167 | |
paul@37 | 168 | /* Configure output compare in single compare (output driven low) mode using |
paul@37 | 169 | Timer2 as time base. The unit is enabled later. It is only really used to |
paul@37 | 170 | achieve precisely-timed level transitions in hardware. */ |
paul@37 | 171 | |
paul@37 | 172 | oc_init(2, 0b010, 2); |
paul@37 | 173 | oc_set_pulse(2, 0); |
paul@37 | 174 | |
paul@47 | 175 | uart_init(1, FPB, 115200); |
paul@37 | 176 | uart_on(1); |
paul@37 | 177 | |
paul@37 | 178 | interrupts_on(); |
paul@37 | 179 | |
paul@37 | 180 | blink(3 << 24, PORTA, 1 << 3); |
paul@37 | 181 | } |
paul@37 | 182 | |
paul@37 | 183 | |
paul@37 | 184 | |
paul@37 | 185 | /* Exception and interrupt handlers. */ |
paul@37 | 186 | |
paul@37 | 187 | void exception_handler(void) |
paul@37 | 188 | { |
paul@37 | 189 | blink(3 << 12, PORTA, 1 << 3); |
paul@37 | 190 | } |
paul@37 | 191 | |
paul@37 | 192 | void interrupt_handler(void) |
paul@37 | 193 | { |
paul@37 | 194 | uint32_t ifs; |
paul@37 | 195 | |
paul@37 | 196 | /* Check for a OC1 interrupt condition. */ |
paul@37 | 197 | |
paul@37 | 198 | ifs = REG(OCIFS) & OC_INT_FLAGS(1, OCxIF); |
paul@37 | 199 | |
paul@37 | 200 | if (ifs) |
paul@37 | 201 | { |
paul@50 | 202 | vga_interrupt_handler(); |
paul@37 | 203 | CLR_REG(OCIFS, ifs); |
paul@37 | 204 | } |
paul@37 | 205 | } |
paul@37 | 206 | |
paul@37 | 207 | |
paul@37 | 208 | |
paul@50 | 209 | /* Enable the channels for the next line. */ |
paul@37 | 210 | |
paul@50 | 211 | void start_visible(vga_display_t *vga_display) |
paul@50 | 212 | { |
paul@50 | 213 | dma_set_source(0, PHYSICAL((uint32_t) vga_display->linedata), |
paul@49 | 214 | display_config.line_length / 2); |
paul@50 | 215 | dma_set_source(2, PHYSICAL((uint32_t) vga_display->linedata + |
paul@50 | 216 | display_config.line_length / 2), |
paul@50 | 217 | display_config.line_length / 2); |
paul@46 | 218 | dma_on(1); |
paul@37 | 219 | } |
paul@37 | 220 | |
paul@50 | 221 | /* Update the channels for the next line. */ |
paul@37 | 222 | |
paul@50 | 223 | void update_visible(vga_display_t *vga_display) |
paul@50 | 224 | { |
paul@50 | 225 | dma_set_source(0, PHYSICAL((uint32_t) vga_display->linedata), |
paul@50 | 226 | display_config.line_length / 2); |
paul@50 | 227 | dma_set_source(2, PHYSICAL((uint32_t) vga_display->linedata + |
paul@50 | 228 | display_config.line_length / 2), |
paul@50 | 229 | display_config.line_length / 2); |
paul@50 | 230 | } |
paul@41 | 231 | |
paul@50 | 232 | /* Disable the channels for the next line. */ |
paul@37 | 233 | |
paul@50 | 234 | void stop_visible(vga_display_t *vga_display) |
paul@50 | 235 | { |
paul@46 | 236 | dma_off(1); |
paul@37 | 237 | } |
paul@37 | 238 | |
paul@50 | 239 | /* Bring vsync low (single compare, output driven low) when the next line |
paul@50 | 240 | starts. */ |
paul@37 | 241 | |
paul@50 | 242 | void vsync_low(void) |
paul@50 | 243 | { |
paul@37 | 244 | oc_init(2, 0b010, 2); |
paul@37 | 245 | oc_on(2); |
paul@37 | 246 | } |
paul@37 | 247 | |
paul@50 | 248 | /* Bring vsync high (single compare, output driven high) when the next line |
paul@50 | 249 | starts. */ |
paul@37 | 250 | |
paul@50 | 251 | void vsync_high(void) |
paul@50 | 252 | { |
paul@37 | 253 | oc_init(2, 0b001, 2); |
paul@37 | 254 | oc_on(2); |
paul@37 | 255 | } |
paul@37 | 256 | |
paul@37 | 257 | |
paul@37 | 258 | |
paul@37 | 259 | /* Peripheral pin configuration. */ |
paul@37 | 260 | |
paul@37 | 261 | void config_oc(void) |
paul@37 | 262 | { |
paul@37 | 263 | /* Map OC1 to RPA0. */ |
paul@37 | 264 | |
paul@37 | 265 | REG(RPA0R) = 0b0101; /* RPA0R<3:0> = 0101 (OC1) */ |
paul@37 | 266 | |
paul@37 | 267 | /* Map OC2 to RPA1. */ |
paul@37 | 268 | |
paul@37 | 269 | REG(RPA1R) = 0b0101; /* RPA1R<3:0> = 0101 (OC2) */ |
paul@37 | 270 | } |
paul@37 | 271 | |
paul@37 | 272 | void config_uart(void) |
paul@37 | 273 | { |
paul@37 | 274 | /* Map U1RX to RPB13. */ |
paul@37 | 275 | |
paul@37 | 276 | REG(U1RXR) = 0b0011; /* U1RXR<3:0> = 0011 (RPB13) */ |
paul@37 | 277 | |
paul@37 | 278 | /* Map U1TX to RPB15. */ |
paul@37 | 279 | |
paul@37 | 280 | REG(RPB15R) = 0b0001; /* RPB15R<3:0> = 0001 (U1TX) */ |
paul@37 | 281 | |
paul@37 | 282 | /* Set RPB13 to input. */ |
paul@37 | 283 | |
paul@37 | 284 | SET_REG(TRISB, 1 << 13); |
paul@37 | 285 | } |