| paul@34 | 1 | /* |
| paul@34 | 2 | * Device configuration. |
| paul@34 | 3 | * |
| paul@34 | 4 | * Copyright (C) 2018 Paul Boddie <paul@boddie.org.uk> |
| paul@34 | 5 | * |
| paul@34 | 6 | * This program is free software: you can redistribute it and/or modify |
| paul@34 | 7 | * it under the terms of the GNU General Public License as published by |
| paul@34 | 8 | * the Free Software Foundation, either version 3 of the License, or |
| paul@34 | 9 | * (at your option) any later version. |
| paul@34 | 10 | * |
| paul@34 | 11 | * This program is distributed in the hope that it will be useful, |
| paul@34 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| paul@34 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| paul@34 | 14 | * GNU General Public License for more details. |
| paul@34 | 15 | * |
| paul@34 | 16 | * You should have received a copy of the GNU General Public License |
| paul@34 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| paul@34 | 18 | */ |
| paul@34 | 19 | |
| paul@34 | 20 | #ifndef __CONFIG_H__ |
| paul@34 | 21 | #define __CONFIG_H__ |
| paul@34 | 22 | |
| paul@34 | 23 | #include "pic32.h" |
| paul@34 | 24 | |
| paul@34 | 25 | /* |
| paul@34 | 26 | Set the oscillator to be the FRC oscillator with PLL, with peripheral clock |
| paul@34 | 27 | divided by 2 (FPBDIV), and FRCDIV+PLL selected (FNOSC). |
| paul@34 | 28 | |
| paul@34 | 29 | The watchdog timer (FWDTEN) is also disabled. |
| paul@34 | 30 | |
| paul@34 | 31 | The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with |
| paul@34 | 32 | RPB4. |
| paul@34 | 33 | */ |
| paul@34 | 34 | |
| paul@34 | 35 | #define DEVCFG1_CONFIG (DEVCFG1_FWDTEN_OFF | DEVCFG1_FPBDIV_2 | \ |
| paul@34 | 36 | DEVCFG1_OSCIOFNC_OFF | DEVCFG1_FSOSCEN_OFF | \ |
| paul@34 | 37 | DEVCFG1_FNOSC_FRCDIV_PLL) |
| paul@34 | 38 | |
| paul@34 | 39 | /* |
| paul@34 | 40 | Set the FRC oscillator PLL function with an input division of 2, an output |
| paul@34 | 41 | division of 2, a multiplication of 24, yielding a multiplication of 6. |
| paul@34 | 42 | |
| paul@34 | 43 | The FRC is apparently at 8MHz but enforces input division of 2 to produce a |
| paul@34 | 44 | frequency in the acceptable range from 4MHz to 5MHz for the PLL: |
| paul@34 | 45 | |
| paul@34 | 46 | 8MHz / 2 = 4MHz |
| paul@34 | 47 | |
| paul@34 | 48 | Multiplication and output division should produce a system clock of 48MHz: |
| paul@34 | 49 | |
| paul@34 | 50 | 4MHz * 24 / 2 = 48MHz |
| paul@34 | 51 | */ |
| paul@34 | 52 | |
| paul@34 | 53 | #define DEVCFG2_CONFIG (DEVCFG2_FPLLODIV_2 | DEVCFG2_FPLLMUL_24 | \ |
| paul@34 | 54 | DEVCFG2_FPLLIDIV_2) |
| paul@34 | 55 | |
| paul@34 | 56 | /* |
| paul@34 | 57 | The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1 and |
| paul@34 | 58 | DEVCFG2 settings. |
| paul@34 | 59 | */ |
| paul@34 | 60 | |
| paul@34 | 61 | #define FPB 24000000 |
| paul@34 | 62 | |
| paul@34 | 63 | #endif /* __CONFIG_H__ */ |
