paul@0 | 1 | /* |
paul@0 | 2 | * PIC32 microcontroller initialisation code. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 5 | * |
paul@0 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@0 | 7 | * it under the terms of the GNU General Public License as published by |
paul@0 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@0 | 9 | * (at your option) any later version. |
paul@0 | 10 | * |
paul@0 | 11 | * This program is distributed in the hope that it will be useful, |
paul@0 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 14 | * GNU General Public License for more details. |
paul@0 | 15 | * |
paul@0 | 16 | * You should have received a copy of the GNU General Public License |
paul@0 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@0 | 18 | */ |
paul@0 | 19 | |
paul@0 | 20 | #include "mips.h" |
paul@0 | 21 | #include "pic32.h" |
paul@0 | 22 | |
paul@0 | 23 | /* Disable JTAG functionality on pins. */ |
paul@0 | 24 | |
paul@0 | 25 | .section .devcfg0, "a" |
paul@0 | 26 | .word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */ |
paul@0 | 27 | |
paul@0 | 28 | /* |
paul@0 | 29 | Set the oscillator to be the FRC oscillator with PLL, with peripheral clock |
paul@0 | 30 | divided by 2, and FRCDIV+PLL selected. |
paul@0 | 31 | |
paul@0 | 32 | The watchdog timer (FWDTEN) is also disabled. |
paul@0 | 33 | |
paul@0 | 34 | The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with |
paul@0 | 35 | RPB4. |
paul@0 | 36 | */ |
paul@0 | 37 | |
paul@0 | 38 | .section .devcfg1, "a" |
paul@0 | 39 | .word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1; |
paul@0 | 40 | DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */ |
paul@0 | 41 | |
paul@0 | 42 | /* |
paul@0 | 43 | Set the FRC oscillator PLL function with an input division of 4, an output |
paul@0 | 44 | division of 2, a multiplication of 24, yielding a multiplication of 3. |
paul@0 | 45 | |
paul@0 | 46 | The FRC is apparently at 16MHz and this produces a system clock of 48MHz. |
paul@4 | 47 | |
paul@4 | 48 | The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1 |
paul@4 | 49 | settings. |
paul@0 | 50 | */ |
paul@0 | 51 | |
paul@0 | 52 | .section .devcfg2, "a" |
paul@0 | 53 | .word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001; |
paul@0 | 54 | DEVCFG2<6:4> = FPLLMUL<2:0> = 111; |
paul@0 | 55 | DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */ |
paul@0 | 56 | |
paul@0 | 57 | /* The start routine is placed at the boot location. */ |
paul@0 | 58 | |
paul@0 | 59 | .section .boot, "a" |
paul@0 | 60 | |
paul@0 | 61 | .globl _start |
paul@0 | 62 | .extern main |
paul@0 | 63 | |
paul@0 | 64 | _start: |
paul@0 | 65 | /* Enable caching. */ |
paul@0 | 66 | |
paul@0 | 67 | mfc0 $v1, CP0_CONFIG |
paul@0 | 68 | li $t8, ~CONFIG_K0 |
paul@0 | 69 | and $v1, $v1, $t8 |
paul@0 | 70 | ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT |
paul@0 | 71 | mtc0 $v1, CP0_CONFIG |
paul@0 | 72 | nop |
paul@0 | 73 | |
paul@0 | 74 | /* Get the RAM size. */ |
paul@0 | 75 | |
paul@0 | 76 | la $v1, BMXDRMSZ |
paul@0 | 77 | lw $t0, 0($v1) |
paul@0 | 78 | |
paul@0 | 79 | /* Initialise the stack pointer. */ |
paul@0 | 80 | |
paul@0 | 81 | li $v1, KSEG0_BASE |
paul@0 | 82 | addu $sp, $t0, $v1 /* sp = KSEG0_BASE + RAM size */ |
paul@0 | 83 | |
paul@0 | 84 | /* Initialise the globals pointer. */ |
paul@0 | 85 | |
paul@0 | 86 | lui $gp, %hi(_GLOBAL_OFFSET_TABLE_) |
paul@0 | 87 | ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_) |
paul@0 | 88 | |
paul@0 | 89 | /* |
paul@0 | 90 | Jump to the main program. Since the boot code is separate from the |
paul@0 | 91 | other code, the address cannot be obtained via the GOT. |
paul@0 | 92 | ("relocation truncated to fit: R_MIPS_PC16 against `main'") |
paul@0 | 93 | */ |
paul@0 | 94 | |
paul@0 | 95 | lui $t9, %hi(main) |
paul@0 | 96 | ori $t9, $t9, %lo(main) |
paul@0 | 97 | jr $t9 |
paul@0 | 98 | nop |