paul@0 | 1 | /* |
paul@0 | 2 | * PIC32 microcontroller interrupt handling code. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 5 | * |
paul@0 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@0 | 7 | * it under the terms of the GNU General Public License as published by |
paul@0 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@0 | 9 | * (at your option) any later version. |
paul@0 | 10 | * |
paul@0 | 11 | * This program is distributed in the hope that it will be useful, |
paul@0 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 14 | * GNU General Public License for more details. |
paul@0 | 15 | * |
paul@0 | 16 | * You should have received a copy of the GNU General Public License |
paul@0 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@0 | 18 | */ |
paul@0 | 19 | |
paul@0 | 20 | #include "mips.h" |
paul@0 | 21 | #include "pic32.h" |
paul@0 | 22 | #include "cpu.h" |
paul@0 | 23 | |
paul@0 | 24 | .globl enable_interrupts |
paul@0 | 25 | .globl handle_error_level |
paul@0 | 26 | .globl init_interrupts |
paul@0 | 27 | .extern exception_handler |
paul@0 | 28 | .extern interrupt_handler |
paul@0 | 29 | |
paul@0 | 30 | /* Put general routines in the text section. */ |
paul@0 | 31 | |
paul@0 | 32 | .text |
paul@0 | 33 | |
paul@0 | 34 | /* |
paul@0 | 35 | Clear the error and exception status flags, making interrupts and exceptions |
paul@0 | 36 | possible. |
paul@0 | 37 | */ |
paul@0 | 38 | |
paul@0 | 39 | handle_error_level: |
paul@0 | 40 | mfc0 $t3, CP0_STATUS |
paul@0 | 41 | |
paul@0 | 42 | /* Clear error level and exception level. */ |
paul@0 | 43 | |
paul@0 | 44 | li $t4, ~(STATUS_ERL | STATUS_EXL) |
paul@0 | 45 | and $t3, $t3, $t4 |
paul@0 | 46 | mtc0 $t3, CP0_STATUS |
paul@0 | 47 | |
paul@0 | 48 | jr $ra |
paul@0 | 49 | nop |
paul@0 | 50 | |
paul@0 | 51 | /* Enable interrupts and direct interrupt requests to non-bootloader vectors. */ |
paul@0 | 52 | |
paul@0 | 53 | enable_interrupts: |
paul@0 | 54 | mfc0 $t3, CP0_STATUS |
paul@0 | 55 | |
paul@0 | 56 | /* Clear interrupt priority bits. */ |
paul@0 | 57 | |
paul@0 | 58 | li $t4, ~STATUS_IRQ |
paul@0 | 59 | and $t3, $t3, $t4 |
paul@0 | 60 | |
paul@0 | 61 | /* Set interrupt priority. */ |
paul@0 | 62 | |
paul@0 | 63 | ori $t3, $t3, (CPU_INT_PRIORITY << STATUS_IRQ_SHIFT) |
paul@0 | 64 | |
paul@0 | 65 | /* CP0_STATUS &= ~STATUS_BEV (use non-bootloader vectors) */ |
paul@0 | 66 | |
paul@0 | 67 | li $t4, ~STATUS_BEV |
paul@0 | 68 | and $t3, $t3, $t4 |
paul@0 | 69 | |
paul@0 | 70 | /* Enable interrupts. */ |
paul@0 | 71 | |
paul@0 | 72 | ori $t3, $t3, STATUS_IE |
paul@0 | 73 | mtc0 $t3, CP0_STATUS |
paul@0 | 74 | |
paul@0 | 75 | jr $ra |
paul@0 | 76 | nop |
paul@0 | 77 | |
paul@0 | 78 | /* Initialise the interrupt system parameters. */ |
paul@0 | 79 | |
paul@0 | 80 | init_interrupts: |
paul@0 | 81 | /* Clear debug mode. */ |
paul@0 | 82 | |
paul@0 | 83 | mfc0 $t3, CP0_DEBUG |
paul@0 | 84 | li $t4, ~DEBUG_DM |
paul@0 | 85 | and $t3, $t3, $t4 |
paul@0 | 86 | mtc0 $t3, CP0_DEBUG |
paul@0 | 87 | |
paul@0 | 88 | /* Update the exception base. */ |
paul@0 | 89 | |
paul@0 | 90 | mfc0 $t3, CP0_STATUS |
paul@0 | 91 | li $t4, STATUS_BEV /* BEV = 1 or EBASE cannot be set */ |
paul@0 | 92 | or $t3, $t3, $t4 |
paul@0 | 93 | mtc0 $t3, CP0_STATUS |
paul@0 | 94 | |
paul@0 | 95 | la $t3, ebase |
paul@0 | 96 | mtc0 $t3, CP0_EBASE |
paul@0 | 97 | |
paul@0 | 98 | /* Set vector spacing. */ |
paul@0 | 99 | |
paul@0 | 100 | li $t3, 0x20 /* Must be non-zero or the CPU gets upset */ |
paul@0 | 101 | mtc0 $t3, CP0_INTCTL |
paul@0 | 102 | |
paul@0 | 103 | li $t3, CAUSE_IV /* IV = 1 (use EBASE+0x200 for interrupts) */ |
paul@0 | 104 | mtc0 $t3, CP0_CAUSE |
paul@0 | 105 | |
paul@0 | 106 | jr $ra |
paul@0 | 107 | nop |
paul@0 | 108 | |
paul@0 | 109 | |
paul@0 | 110 | |
paul@0 | 111 | /* Exception servicing, positioned at EBASE at the start of program memory. */ |
paul@0 | 112 | |
paul@0 | 113 | .section .vectors, "a" |
paul@0 | 114 | |
paul@0 | 115 | /* TLB error servicing. */ |
paul@0 | 116 | |
paul@0 | 117 | ebase: |
paul@0 | 118 | tlb_handler: |
paul@0 | 119 | j exception_handler |
paul@0 | 120 | nop |
paul@0 | 121 | |
paul@0 | 122 | |
paul@0 | 123 | |
paul@0 | 124 | /* General exception servicing. */ |
paul@0 | 125 | |
paul@0 | 126 | .org 0x180 |
paul@0 | 127 | |
paul@0 | 128 | exc_handler: |
paul@0 | 129 | j exception_handler |
paul@0 | 130 | nop |
paul@0 | 131 | |
paul@0 | 132 | |
paul@0 | 133 | |
paul@0 | 134 | /* Interrupt servicing. */ |
paul@0 | 135 | |
paul@0 | 136 | .org 0x200 |
paul@0 | 137 | .set noat |
paul@0 | 138 | |
paul@22 | 139 | #define IRQ_STACK_LIMIT (KSEG0_BASE + IRQ_STACK_SIZE) |
paul@0 | 140 | #define IRQ_STACK_TOP (IRQ_STACK_LIMIT - 32 * 4) |
paul@0 | 141 | |
paul@0 | 142 | int_handler: |
paul@0 | 143 | |
paul@0 | 144 | /* Store affected registers from IRQ_STACK_LIMIT - 4 downwards. */ |
paul@0 | 145 | |
paul@22 | 146 | lui $k0, %hi(IRQ_STACK_LIMIT) |
paul@22 | 147 | ori $k0, $k0, %lo(IRQ_STACK_LIMIT) |
paul@0 | 148 | |
paul@0 | 149 | .irp reg, \ |
paul@0 | 150 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 \ |
paul@0 | 151 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \ |
paul@0 | 152 | 28, 29, 30, 31 |
paul@0 | 153 | sw $\reg, -(\reg * 4)($k0) |
paul@0 | 154 | .endr |
paul@0 | 155 | |
paul@0 | 156 | /* Switch to the IRQ stack. */ |
paul@0 | 157 | |
paul@22 | 158 | lui $sp, %hi(IRQ_STACK_TOP) |
paul@22 | 159 | ori $sp, $sp, %lo(IRQ_STACK_TOP) |
paul@0 | 160 | |
paul@0 | 161 | jal interrupt_handler |
paul@0 | 162 | nop |
paul@0 | 163 | |
paul@0 | 164 | /* Restore affected registers. */ |
paul@0 | 165 | |
paul@0 | 166 | .irp reg, \ |
paul@0 | 167 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 \ |
paul@0 | 168 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \ |
paul@0 | 169 | 28, 29, 30, 31 |
paul@0 | 170 | lw $\reg, -(\reg * 4)($k0) |
paul@0 | 171 | .endr |
paul@0 | 172 | |
paul@0 | 173 | eret |
paul@0 | 174 | nop |