paul@15 | 1 | /* |
paul@15 | 2 | * PIC32 peripheral configuration and initialisation. |
paul@15 | 3 | * |
paul@15 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@15 | 5 | * |
paul@15 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@15 | 7 | * it under the terms of the GNU General Public License as published by |
paul@15 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@15 | 9 | * (at your option) any later version. |
paul@15 | 10 | * |
paul@15 | 11 | * This program is distributed in the hope that it will be useful, |
paul@15 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@15 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@15 | 14 | * GNU General Public License for more details. |
paul@15 | 15 | * |
paul@15 | 16 | * You should have received a copy of the GNU General Public License |
paul@15 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@15 | 18 | */ |
paul@15 | 19 | |
paul@0 | 20 | #include "cpu.h" |
paul@0 | 21 | #include "pic32_c.h" |
paul@3 | 22 | #include "init.h" |
paul@0 | 23 | |
paul@34 | 24 | /* Application-specific configuration. */ |
paul@34 | 25 | |
paul@34 | 26 | #include "devconfig.h" |
paul@34 | 27 | |
paul@0 | 28 | |
paul@0 | 29 | |
paul@0 | 30 | /* Basic memory and pin initialisation. */ |
paul@0 | 31 | |
paul@0 | 32 | void init_memory(void) |
paul@0 | 33 | { |
paul@0 | 34 | /* |
paul@0 | 35 | Configure RAM. |
paul@0 | 36 | See: http://microchipdeveloper.com/32bit:mx-arch-exceptions-processor-initialization |
paul@0 | 37 | */ |
paul@0 | 38 | |
paul@0 | 39 | uint32_t config = REG(BMXCON); |
paul@0 | 40 | |
paul@0 | 41 | /* Set zero wait states for address setup. */ |
paul@0 | 42 | |
paul@0 | 43 | config &= ~(1 << 6); /* BMXCON<6> = BMXWSDRM = 0 */ |
paul@0 | 44 | |
paul@0 | 45 | /* Set bus arbitration mode. */ |
paul@0 | 46 | |
paul@0 | 47 | config &= ~0b111; |
paul@0 | 48 | config |= 0b010; /* BMXCON<2:0> = BMXARB<2:0> = 2 */ |
paul@0 | 49 | |
paul@0 | 50 | REG(BMXCON) = config; |
paul@0 | 51 | } |
paul@0 | 52 | |
paul@0 | 53 | void init_pins(void) |
paul@0 | 54 | { |
paul@0 | 55 | /* DEVCFG0<2> also needs setting to 0 before the program is run. */ |
paul@0 | 56 | |
paul@0 | 57 | CLR_REG(CFGCON, 1 << 3); /* CFGCON<3> = JTAGEN = 0 */ |
paul@0 | 58 | } |
paul@0 | 59 | |
paul@0 | 60 | void init_outputs(void) |
paul@0 | 61 | { |
paul@0 | 62 | /* Remove analogue features from pins. */ |
paul@0 | 63 | |
paul@0 | 64 | REG(ANSELA) = 0; |
paul@0 | 65 | REG(ANSELB) = 0; |
paul@0 | 66 | |
paul@3 | 67 | /* Set pins as outputs. */ |
paul@3 | 68 | |
paul@0 | 69 | REG(TRISA) = 0; |
paul@0 | 70 | REG(TRISB) = 0; |
paul@0 | 71 | |
paul@3 | 72 | /* Clear outputs. */ |
paul@3 | 73 | |
paul@0 | 74 | REG(PORTA) = 0; |
paul@0 | 75 | REG(PORTB) = 0; |
paul@0 | 76 | } |
paul@0 | 77 | |
paul@0 | 78 | |
paul@0 | 79 | |
paul@0 | 80 | /* Peripheral pin configuration. */ |
paul@0 | 81 | |
paul@0 | 82 | void lock_config(void) |
paul@0 | 83 | { |
paul@0 | 84 | SET_REG(CFGCON, 1 << 13); /* IOLOCK = 1 */ |
paul@0 | 85 | |
paul@0 | 86 | /* Lock the configuration again. */ |
paul@0 | 87 | |
paul@0 | 88 | REG(SYSKEY) = 0x33333333; |
paul@0 | 89 | } |
paul@0 | 90 | |
paul@0 | 91 | void unlock_config(void) |
paul@0 | 92 | { |
paul@0 | 93 | /* Unlock the configuration register bits. */ |
paul@0 | 94 | |
paul@0 | 95 | REG(SYSKEY) = 0; |
paul@0 | 96 | REG(SYSKEY) = 0xAA996655; |
paul@0 | 97 | REG(SYSKEY) = 0x556699AA; |
paul@0 | 98 | |
paul@0 | 99 | CLR_REG(CFGCON, 1 << 13); /* IOLOCK = 0 */ |
paul@0 | 100 | } |
paul@0 | 101 | |
paul@0 | 102 | |
paul@0 | 103 | |
paul@0 | 104 | /* Convenience operations. */ |
paul@0 | 105 | |
paul@0 | 106 | void interrupts_on(void) |
paul@0 | 107 | { |
paul@0 | 108 | init_interrupts(); |
paul@0 | 109 | enable_interrupts(); |
paul@0 | 110 | handle_error_level(); |
paul@0 | 111 | } |
paul@0 | 112 | |
paul@0 | 113 | |
paul@0 | 114 | |
paul@3 | 115 | /* DMA configuration. */ |
paul@3 | 116 | |
paul@3 | 117 | void init_dma(void) |
paul@3 | 118 | { |
paul@32 | 119 | /* Disable DMA interrupts (DMAxIE). */ |
paul@3 | 120 | |
paul@32 | 121 | CLR_REG(DMAIEC, 0b1111 << DMAINTBASE); |
paul@3 | 122 | |
paul@32 | 123 | /* Clear DMA interrupt flags (DMAxIF). */ |
paul@3 | 124 | |
paul@32 | 125 | CLR_REG(DMAIFS, 0b1111 << DMAINTBASE); |
paul@3 | 126 | |
paul@3 | 127 | /* Enable DMA. */ |
paul@3 | 128 | |
paul@3 | 129 | SET_REG(DMACON, 1 << 15); |
paul@3 | 130 | } |
paul@3 | 131 | |
paul@3 | 132 | /* Initialise the given channel. */ |
paul@0 | 133 | |
paul@10 | 134 | void dma_init(int channel, uint8_t pri) |
paul@0 | 135 | { |
paul@7 | 136 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@3 | 137 | return; |
paul@3 | 138 | |
paul@3 | 139 | /* Initialise a channel. */ |
paul@3 | 140 | |
paul@10 | 141 | REG(DMA_REG(channel, DCHxCON)) = pri & 0b11; |
paul@3 | 142 | REG(DMA_REG(channel, DCHxECON)) = 0; |
paul@3 | 143 | REG(DMA_REG(channel, DCHxINT)) = 0; |
paul@3 | 144 | } |
paul@3 | 145 | |
paul@23 | 146 | /* Set the channel repeated enable mode, enabling it again when a block transfer |
paul@23 | 147 | completes. The documentation describes this as auto-enable. */ |
paul@10 | 148 | |
paul@23 | 149 | void dma_set_auto_enable(int channel, int enable) |
paul@10 | 150 | { |
paul@23 | 151 | (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 4); |
paul@10 | 152 | } |
paul@10 | 153 | |
paul@10 | 154 | /* Set the channel chaining mode. */ |
paul@10 | 155 | |
paul@10 | 156 | void dma_set_chaining(int channel, enum dma_chain chain) |
paul@10 | 157 | { |
paul@10 | 158 | (chain != dma_chain_none ? |
paul@10 | 159 | SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 5); |
paul@10 | 160 | |
paul@10 | 161 | (chain == dma_chain_next ? |
paul@10 | 162 | SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 8); |
paul@10 | 163 | } |
paul@10 | 164 | |
paul@3 | 165 | /* Configure a channel's initiation interrupt. */ |
paul@3 | 166 | |
paul@3 | 167 | void dma_set_interrupt(int channel, uint8_t int_num, int enable) |
paul@3 | 168 | { |
paul@7 | 169 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@3 | 170 | return; |
paul@0 | 171 | |
paul@3 | 172 | /* Allow an interrupt to trigger the transfer. */ |
paul@3 | 173 | |
paul@3 | 174 | REG(DMA_REG(channel, DCHxECON)) = (int_num << 8) | |
paul@3 | 175 | ((enable ? 1 : 0) << 4); |
paul@3 | 176 | } |
paul@3 | 177 | |
paul@23 | 178 | /* Configure only the channel's initiation interrupt status. */ |
paul@23 | 179 | |
paul@23 | 180 | void dma_set_interrupt_enable(int channel, int enable) |
paul@23 | 181 | { |
paul@23 | 182 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@23 | 183 | return; |
paul@23 | 184 | |
paul@23 | 185 | (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxECON), 1 << 4); |
paul@23 | 186 | } |
paul@23 | 187 | |
paul@23 | 188 | /* Permit the channel to register events while disabled or suspended. A |
paul@23 | 189 | suspended channel is one that is enabled but where the DMA peripheral |
paul@23 | 190 | has been suspended. */ |
paul@23 | 191 | |
paul@23 | 192 | void dma_set_receive_events(int channel, int enable) |
paul@23 | 193 | { |
paul@23 | 194 | (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 6); |
paul@23 | 195 | } |
paul@23 | 196 | |
paul@39 | 197 | /* Set a channel's source. */ |
paul@39 | 198 | |
paul@39 | 199 | void dma_set_source(int channel, |
paul@39 | 200 | uint32_t source_start_address, uint16_t source_size) |
paul@39 | 201 | { |
paul@39 | 202 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@39 | 203 | return; |
paul@39 | 204 | |
paul@39 | 205 | REG(DMA_REG(channel, DCHxSSIZ)) = source_size; |
paul@39 | 206 | REG(DMA_REG(channel, DCHxSSA)) = source_start_address; |
paul@39 | 207 | } |
paul@39 | 208 | |
paul@3 | 209 | /* Set a channel's transfer parameters. */ |
paul@3 | 210 | |
paul@3 | 211 | void dma_set_transfer(int channel, |
paul@3 | 212 | uint32_t source_start_address, uint16_t source_size, |
paul@3 | 213 | uint32_t destination_start_address, uint16_t destination_size, |
paul@3 | 214 | uint16_t cell_size) |
paul@3 | 215 | { |
paul@7 | 216 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@3 | 217 | return; |
paul@0 | 218 | |
paul@39 | 219 | dma_set_source(channel, source_start_address, source_size); |
paul@39 | 220 | |
paul@3 | 221 | REG(DMA_REG(channel, DCHxDSIZ)) = destination_size; |
paul@3 | 222 | REG(DMA_REG(channel, DCHxDSA)) = destination_start_address; |
paul@3 | 223 | REG(DMA_REG(channel, DCHxCSIZ)) = cell_size; |
paul@3 | 224 | } |
paul@3 | 225 | |
paul@3 | 226 | /* Configure interrupts caused by the channel. */ |
paul@0 | 227 | |
paul@3 | 228 | void dma_init_interrupt(int channel, uint8_t conditions, |
paul@7 | 229 | uint8_t pri, uint8_t sub) |
paul@3 | 230 | { |
paul@7 | 231 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@3 | 232 | return; |
paul@0 | 233 | |
paul@10 | 234 | /* Disable channel interrupt and clear interrupt flag. */ |
paul@10 | 235 | |
paul@10 | 236 | CLR_REG(DMAIEC, DMA_INT_FLAGS(channel, 1)); |
paul@10 | 237 | CLR_REG(DMAIFS, DMA_INT_FLAGS(channel, 1)); |
paul@10 | 238 | |
paul@3 | 239 | /* Produce an interrupt for the provided conditions. */ |
paul@3 | 240 | |
paul@3 | 241 | REG(DMA_REG(channel, DCHxINT)) = conditions << 16; |
paul@3 | 242 | |
paul@3 | 243 | /* Set interrupt priorities. */ |
paul@3 | 244 | |
paul@14 | 245 | REG(DMAIPC) = (REG(DMAIPC) & |
paul@14 | 246 | ~(DMA_IPC_PRI(channel, 7, 3))) | |
paul@7 | 247 | DMA_IPC_PRI(channel, pri, sub); |
paul@0 | 248 | |
paul@0 | 249 | /* Enable interrupt. */ |
paul@0 | 250 | |
paul@10 | 251 | SET_REG(DMAIEC, DMA_INT_FLAGS(channel, 1)); |
paul@3 | 252 | } |
paul@3 | 253 | |
paul@23 | 254 | /* Enable or disable the channel. */ |
paul@23 | 255 | |
paul@23 | 256 | void dma_set_enable(int channel, int enable) |
paul@23 | 257 | { |
paul@23 | 258 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@23 | 259 | return; |
paul@23 | 260 | |
paul@23 | 261 | (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 7); |
paul@23 | 262 | } |
paul@23 | 263 | |
paul@23 | 264 | /* Disable a DMA channel. */ |
paul@23 | 265 | |
paul@23 | 266 | void dma_off(int channel) |
paul@23 | 267 | { |
paul@23 | 268 | dma_set_enable(channel, 0); |
paul@23 | 269 | } |
paul@23 | 270 | |
paul@3 | 271 | /* Enable a DMA channel. */ |
paul@3 | 272 | |
paul@3 | 273 | void dma_on(int channel) |
paul@3 | 274 | { |
paul@23 | 275 | dma_set_enable(channel, 1); |
paul@3 | 276 | } |
paul@3 | 277 | |
paul@7 | 278 | |
paul@7 | 279 | |
paul@29 | 280 | /* External interrupt initialisation. */ |
paul@29 | 281 | |
paul@29 | 282 | void int_init_interrupt(int int_num, uint8_t pri, uint8_t sub) |
paul@29 | 283 | { |
paul@29 | 284 | if ((int_num < INTMIN) || (int_num > INTMAX)) |
paul@29 | 285 | return; |
paul@29 | 286 | |
paul@29 | 287 | /* Disable interrupt and clear interrupt flag. */ |
paul@29 | 288 | |
paul@29 | 289 | CLR_REG(INTIEC, INT_INT_FLAGS(int_num, INTxIE)); |
paul@29 | 290 | CLR_REG(INTIFS, INT_INT_FLAGS(int_num, INTxIF)); |
paul@29 | 291 | |
paul@29 | 292 | /* Set interrupt priorities. */ |
paul@29 | 293 | |
paul@29 | 294 | REG(INT_IPC_REG(int_num)) = (REG(INT_IPC_REG(int_num)) & |
paul@29 | 295 | ~(INT_IPC_PRI(int_num, 7, 3))) | |
paul@29 | 296 | INT_IPC_PRI(int_num, pri, sub); |
paul@29 | 297 | |
paul@29 | 298 | /* Enable interrupt. */ |
paul@29 | 299 | |
paul@29 | 300 | SET_REG(INTIEC, INT_INT_FLAGS(int_num, INTxIE)); |
paul@29 | 301 | } |
paul@29 | 302 | |
paul@29 | 303 | |
paul@29 | 304 | |
paul@14 | 305 | /* Output compare configuration. */ |
paul@14 | 306 | |
paul@14 | 307 | void oc_init(int unit, uint8_t mode, int timer) |
paul@14 | 308 | { |
paul@14 | 309 | if ((unit < OCMIN) || (unit > OCMAX)) |
paul@14 | 310 | return; |
paul@14 | 311 | |
paul@14 | 312 | REG(OC_REG(unit, OCxCON)) = (timer == 3 ? (1 << 3) : 0) | (mode & 0b111); |
paul@14 | 313 | } |
paul@14 | 314 | |
paul@14 | 315 | /* Set the start value for the pulse. */ |
paul@14 | 316 | |
paul@14 | 317 | void oc_set_pulse(int unit, uint32_t start) |
paul@14 | 318 | { |
paul@14 | 319 | if ((unit < OCMIN) || (unit > OCMAX)) |
paul@14 | 320 | return; |
paul@14 | 321 | |
paul@14 | 322 | REG(OC_REG(unit, OCxR)) = start; |
paul@14 | 323 | } |
paul@14 | 324 | |
paul@14 | 325 | /* Set the end value for the pulse. */ |
paul@14 | 326 | |
paul@14 | 327 | void oc_set_pulse_end(int unit, uint32_t end) |
paul@14 | 328 | { |
paul@14 | 329 | if ((unit < OCMIN) || (unit > OCMAX)) |
paul@14 | 330 | return; |
paul@14 | 331 | |
paul@14 | 332 | REG(OC_REG(unit, OCxRS)) = end; |
paul@14 | 333 | } |
paul@14 | 334 | |
paul@14 | 335 | /* Configure interrupts caused by the unit. */ |
paul@14 | 336 | |
paul@14 | 337 | void oc_init_interrupt(int unit, uint8_t pri, uint8_t sub) |
paul@14 | 338 | { |
paul@14 | 339 | if ((unit < OCMIN) || (unit > OCMAX)) |
paul@14 | 340 | return; |
paul@14 | 341 | |
paul@14 | 342 | /* Disable interrupt and clear interrupt flag. */ |
paul@14 | 343 | |
paul@14 | 344 | CLR_REG(OCIEC, OC_INT_FLAGS(unit, OCxIE)); |
paul@14 | 345 | CLR_REG(OCIFS, OC_INT_FLAGS(unit, OCxIF)); |
paul@14 | 346 | |
paul@14 | 347 | /* Set interrupt priorities. */ |
paul@14 | 348 | |
paul@14 | 349 | REG(OC_IPC_REG(unit)) = (REG(OC_IPC_REG(unit)) & |
paul@14 | 350 | ~(OC_IPC_PRI(unit, 7, 3))) | |
paul@14 | 351 | OC_IPC_PRI(unit, pri, sub); |
paul@14 | 352 | |
paul@14 | 353 | /* Enable interrupt. */ |
paul@14 | 354 | |
paul@14 | 355 | SET_REG(OCIEC, OC_INT_FLAGS(unit, OCxIE)); |
paul@14 | 356 | } |
paul@14 | 357 | |
paul@14 | 358 | /* Enable a unit. */ |
paul@14 | 359 | |
paul@14 | 360 | void oc_on(int unit) |
paul@14 | 361 | { |
paul@14 | 362 | if ((unit < OCMIN) || (unit > OCMAX)) |
paul@14 | 363 | return; |
paul@14 | 364 | |
paul@14 | 365 | SET_REG(OC_REG(unit, OCxCON), 1 << 15); |
paul@14 | 366 | } |
paul@14 | 367 | |
paul@14 | 368 | |
paul@14 | 369 | |
paul@32 | 370 | /* Parallel mode configuration. */ |
paul@32 | 371 | |
paul@32 | 372 | void init_pm(void) |
paul@32 | 373 | { |
paul@32 | 374 | int i; |
paul@32 | 375 | |
paul@32 | 376 | /* Disable PM interrupts (PMxIE). */ |
paul@32 | 377 | |
paul@32 | 378 | CLR_REG(PMIEC, 0b11 << PMINTBASE); |
paul@32 | 379 | |
paul@32 | 380 | /* Clear PM interrupt flags (PMxIF). */ |
paul@32 | 381 | |
paul@32 | 382 | CLR_REG(PMIFS, 0b11 << PMINTBASE); |
paul@32 | 383 | |
paul@32 | 384 | /* Disable PM for configuration. */ |
paul@32 | 385 | |
paul@32 | 386 | for (i = PMMIN; i <= PMMAX; i++) |
paul@32 | 387 | REG(PM_REG(i, PMxCON)) = 0; |
paul@32 | 388 | } |
paul@32 | 389 | |
paul@32 | 390 | /* Configure the parallel mode. */ |
paul@32 | 391 | |
paul@32 | 392 | void pm_init(int port, uint8_t mode) |
paul@32 | 393 | { |
paul@32 | 394 | if ((port < PMMIN) || (port > PMMAX)) |
paul@32 | 395 | return; |
paul@32 | 396 | |
paul@32 | 397 | REG(PM_REG(port, PMxMODE)) = (mode & 0b11) << 8; |
paul@32 | 398 | REG(PM_REG(port, PMxAEN)) = 0; |
paul@32 | 399 | REG(PM_REG(port, PMxADDR)) = 0; |
paul@32 | 400 | } |
paul@32 | 401 | |
paul@32 | 402 | /* Configure output signals. */ |
paul@32 | 403 | |
paul@32 | 404 | void pm_set_output(int port, int write_enable, int read_enable) |
paul@32 | 405 | { |
paul@32 | 406 | if ((port < PMMIN) || (port > PMMAX)) |
paul@32 | 407 | return; |
paul@32 | 408 | |
paul@32 | 409 | REG(PM_REG(port, PMxCON)) = (write_enable ? (1 << 9) : 0) | |
paul@33 | 410 | (read_enable ? (1 << 8) : 0) | |
paul@33 | 411 | (1 << 1); /* WRSP: PMENB active high */ |
paul@32 | 412 | } |
paul@32 | 413 | |
paul@32 | 414 | /* Configure interrupts caused by parallel mode. */ |
paul@32 | 415 | |
paul@32 | 416 | void pm_init_interrupt(int port, uint8_t pri, uint8_t sub) |
paul@32 | 417 | { |
paul@32 | 418 | if ((port < PMMIN) || (port > PMMAX)) |
paul@32 | 419 | return; |
paul@32 | 420 | |
paul@32 | 421 | /* Disable interrupt and clear interrupt flag. */ |
paul@32 | 422 | |
paul@32 | 423 | CLR_REG(PMIEC, PM_INT_FLAGS(port, PMxIE)); |
paul@32 | 424 | CLR_REG(PMIFS, PM_INT_FLAGS(port, PMxIF)); |
paul@32 | 425 | |
paul@32 | 426 | /* Set interrupt priorities. */ |
paul@32 | 427 | |
paul@32 | 428 | REG(PM_IPC_REG(port)) = (REG(PM_IPC_REG(port)) & |
paul@32 | 429 | ~(PM_IPC_PRI(port, 7, 3))) | |
paul@32 | 430 | PM_IPC_PRI(port, pri, sub); |
paul@32 | 431 | |
paul@32 | 432 | /* Enable interrupt. */ |
paul@32 | 433 | |
paul@32 | 434 | SET_REG(PMIEC, PM_INT_FLAGS(port, PMxIE)); |
paul@32 | 435 | } |
paul@32 | 436 | |
paul@32 | 437 | /* Enable parallel mode. */ |
paul@32 | 438 | |
paul@32 | 439 | void pm_on(int port) |
paul@32 | 440 | { |
paul@32 | 441 | if ((port < PMMIN) || (port > PMMAX)) |
paul@32 | 442 | return; |
paul@32 | 443 | |
paul@32 | 444 | SET_REG(PM_REG(port, PMxCON), 1 << 15); |
paul@32 | 445 | } |
paul@32 | 446 | |
paul@32 | 447 | /* Disable parallel mode. */ |
paul@32 | 448 | |
paul@32 | 449 | void pm_off(int port) |
paul@32 | 450 | { |
paul@32 | 451 | if ((port < PMMIN) || (port > PMMAX)) |
paul@32 | 452 | return; |
paul@32 | 453 | |
paul@32 | 454 | CLR_REG(PM_REG(port, PMxCON), 1 << 15); |
paul@32 | 455 | } |
paul@32 | 456 | |
paul@32 | 457 | |
paul@32 | 458 | |
paul@32 | 459 | |
paul@7 | 460 | /* Timer configuration. */ |
paul@7 | 461 | |
paul@7 | 462 | void timer_init(int timer, uint8_t prescale, uint16_t limit) |
paul@7 | 463 | { |
paul@7 | 464 | /* NOTE: Should convert from the real prescale value. */ |
paul@7 | 465 | |
paul@7 | 466 | REG(TIMER_REG(timer, TxCON)) = (prescale & 0b111) << 4; |
paul@7 | 467 | REG(TIMER_REG(timer, TMRx)) = 0; |
paul@7 | 468 | REG(TIMER_REG(timer, PRx)) = limit; |
paul@7 | 469 | } |
paul@7 | 470 | |
paul@7 | 471 | /* Configure interrupts caused by the timer. */ |
paul@7 | 472 | |
paul@7 | 473 | void timer_init_interrupt(int timer, uint8_t pri, uint8_t sub) |
paul@7 | 474 | { |
paul@7 | 475 | if ((timer < TIMERMIN) || (timer > TIMERMAX)) |
paul@7 | 476 | return; |
paul@7 | 477 | |
paul@14 | 478 | /* Disable interrupt and clear interrupt flag. */ |
paul@14 | 479 | |
paul@14 | 480 | CLR_REG(TIMERIEC, TIMER_INT_FLAGS(timer, TxIE)); |
paul@14 | 481 | CLR_REG(TIMERIFS, TIMER_INT_FLAGS(timer, TxIF)); |
paul@14 | 482 | |
paul@7 | 483 | /* Set interrupt priorities. */ |
paul@7 | 484 | |
paul@7 | 485 | REG(TIMER_IPC_REG(timer)) = (REG(TIMER_IPC_REG(timer)) & |
paul@7 | 486 | ~(TIMER_IPC_PRI(timer, 7, 3))) | |
paul@7 | 487 | TIMER_IPC_PRI(timer, pri, sub); |
paul@7 | 488 | |
paul@7 | 489 | /* Enable interrupt. */ |
paul@7 | 490 | |
paul@7 | 491 | SET_REG(TIMERIEC, TIMER_INT_FLAGS(timer, TxIE)); |
paul@7 | 492 | } |
paul@7 | 493 | |
paul@7 | 494 | /* Enable a timer. */ |
paul@7 | 495 | |
paul@7 | 496 | void timer_on(int timer) |
paul@7 | 497 | { |
paul@7 | 498 | if ((timer < TIMERMIN) || (timer > TIMERMAX)) |
paul@7 | 499 | return; |
paul@7 | 500 | |
paul@7 | 501 | SET_REG(TIMER_REG(timer, TxCON), 1 << 15); |
paul@7 | 502 | } |
paul@7 | 503 | |
paul@7 | 504 | |
paul@7 | 505 | |
paul@3 | 506 | /* UART configuration. */ |
paul@3 | 507 | |
paul@7 | 508 | void uart_init(int uart, uint32_t baudrate) |
paul@3 | 509 | { |
paul@34 | 510 | /* FPB is configured in the devconfig.h file and set in the start.S file. */ |
paul@3 | 511 | |
paul@7 | 512 | if ((uart < UARTMIN) || (uart > UARTMAX)) |
paul@3 | 513 | return; |
paul@3 | 514 | |
paul@3 | 515 | /* Disable the UART (ON). */ |
paul@3 | 516 | |
paul@7 | 517 | CLR_REG(UART_REG(uart, UxMODE), 1 << 15); |
paul@3 | 518 | |
paul@3 | 519 | /* Set the baud rate. For example: |
paul@3 | 520 | |
paul@3 | 521 | UxBRG<15:0> = BRG |
paul@3 | 522 | = (FPB / (16 * baudrate)) - 1 |
paul@3 | 523 | = (24000000 / (16 * 115200)) - 1 |
paul@3 | 524 | = 12 |
paul@3 | 525 | */ |
paul@3 | 526 | |
paul@7 | 527 | REG(UART_REG(uart, UxBRG)) = (FPB / (16 * baudrate)) - 1; |
paul@3 | 528 | } |
paul@3 | 529 | |
paul@3 | 530 | /* Configure interrupts caused by the UART. */ |
paul@3 | 531 | |
paul@7 | 532 | void uart_init_interrupt(int uart, uint8_t conditions, |
paul@7 | 533 | uint8_t pri, uint8_t sub) |
paul@3 | 534 | { |
paul@7 | 535 | if ((uart < UARTMIN) || (uart > UARTMAX)) |
paul@3 | 536 | return; |
paul@3 | 537 | |
paul@14 | 538 | /* Disable interrupts and clear interrupt flags. */ |
paul@14 | 539 | |
paul@14 | 540 | CLR_REG(UARTIEC, UART_INT_FLAGS(uart, UxTIE | UxRIE | UxEIE)); |
paul@14 | 541 | CLR_REG(UARTIFS, UART_INT_FLAGS(uart, UxTIF | UxRIF | UxEIF)); |
paul@14 | 542 | |
paul@3 | 543 | /* Set priorities: UxIP = pri; UxIS = sub */ |
paul@3 | 544 | |
paul@14 | 545 | REG(UART_IPC_REG(uart)) = (REG(UART_IPC_REG(uart)) & |
paul@14 | 546 | ~UART_IPC_PRI(uart, 7, 3)) | |
paul@14 | 547 | UART_IPC_PRI(uart, pri, sub); |
paul@3 | 548 | |
paul@7 | 549 | /* Enable interrupts. */ |
paul@3 | 550 | |
paul@7 | 551 | SET_REG(UARTIEC, UART_INT_FLAGS(uart, conditions)); |
paul@3 | 552 | } |
paul@3 | 553 | |
paul@3 | 554 | /* Enable a UART. */ |
paul@3 | 555 | |
paul@7 | 556 | void uart_on(int uart) |
paul@3 | 557 | { |
paul@7 | 558 | if ((uart < UARTMIN) || (uart > UARTMAX)) |
paul@3 | 559 | return; |
paul@3 | 560 | |
paul@3 | 561 | /* Enable receive (URXEN) and transmit (UTXEN). */ |
paul@3 | 562 | |
paul@7 | 563 | SET_REG(UART_REG(uart, UxSTA), (1 << 12) | (1 << 10)); |
paul@0 | 564 | |
paul@0 | 565 | /* Start UART. */ |
paul@0 | 566 | |
paul@7 | 567 | SET_REG(UART_REG(uart, UxMODE), 1 << 15); |
paul@3 | 568 | } |
paul@3 | 569 | |
paul@3 | 570 | |
paul@3 | 571 | |
paul@3 | 572 | /* Utility functions. */ |
paul@3 | 573 | |
paul@3 | 574 | /* Return encoded interrupt priorities. */ |
paul@3 | 575 | |
paul@3 | 576 | static uint8_t PRI(uint8_t pri, uint8_t sub) |
paul@3 | 577 | { |
paul@3 | 578 | return ((pri & 0b111) << 2) | (sub & 0b11); |
paul@3 | 579 | } |
paul@3 | 580 | |
paul@10 | 581 | /* Return the DMA interrupt flags for combining with a register. */ |
paul@10 | 582 | |
paul@10 | 583 | int DMA_INT_FLAGS(int channel, uint8_t flags) |
paul@10 | 584 | { |
paul@10 | 585 | return (flags & 0b1) << (DMAINTBASE + (channel - DCHMIN)); |
paul@10 | 586 | } |
paul@10 | 587 | |
paul@3 | 588 | /* Return encoded DMA interrupt priorities for combining with a register. */ |
paul@3 | 589 | |
paul@3 | 590 | uint32_t DMA_IPC_PRI(int channel, uint8_t pri, uint8_t sub) |
paul@3 | 591 | { |
paul@3 | 592 | return PRI(pri, sub) << (DCHIPCBASE + (channel - DCHMIN) * DCHIPCSTEP); |
paul@0 | 593 | } |
paul@3 | 594 | |
paul@29 | 595 | /* Return encoded external interrupt priorities for combining with a register. */ |
paul@29 | 596 | |
paul@29 | 597 | uint32_t INT_IPC_PRI(int int_num, uint8_t pri, uint8_t sub) |
paul@29 | 598 | { |
paul@29 | 599 | (void) int_num; |
paul@29 | 600 | return PRI(pri, sub) << INTIPCBASE; |
paul@29 | 601 | } |
paul@29 | 602 | |
paul@29 | 603 | /* Return the external interrupt priorities register. */ |
paul@29 | 604 | |
paul@29 | 605 | uint32_t INT_IPC_REG(int int_num) |
paul@29 | 606 | { |
paul@29 | 607 | switch (int_num) |
paul@29 | 608 | { |
paul@29 | 609 | case 0: return INT0IPC; |
paul@29 | 610 | case 1: return INT1IPC; |
paul@29 | 611 | case 2: return INT2IPC; |
paul@29 | 612 | case 3: return INT3IPC; |
paul@29 | 613 | case 4: return INT4IPC; |
paul@29 | 614 | default: return 0; /* should not occur */ |
paul@29 | 615 | } |
paul@29 | 616 | } |
paul@29 | 617 | |
paul@29 | 618 | /* Return the external interrupt flags for combining with a register. */ |
paul@29 | 619 | |
paul@29 | 620 | int INT_INT_FLAGS(int int_num, uint8_t flags) |
paul@29 | 621 | { |
paul@29 | 622 | return (flags & 0b1) << (INTINTBASE + (int_num - INTMIN) * INTINTSTEP); |
paul@29 | 623 | } |
paul@29 | 624 | |
paul@14 | 625 | /* Return encoded output compare interrupt priorities for combining with a register. */ |
paul@14 | 626 | |
paul@14 | 627 | uint32_t OC_IPC_PRI(int unit, uint8_t pri, uint8_t sub) |
paul@14 | 628 | { |
paul@14 | 629 | (void) unit; |
paul@14 | 630 | return PRI(pri, sub) << OCIPCBASE; |
paul@14 | 631 | } |
paul@14 | 632 | |
paul@14 | 633 | /* Return the output compare interrupt priorities register. */ |
paul@14 | 634 | |
paul@14 | 635 | uint32_t OC_IPC_REG(int unit) |
paul@14 | 636 | { |
paul@14 | 637 | switch (unit) |
paul@14 | 638 | { |
paul@14 | 639 | case 1: return OC1IPC; |
paul@14 | 640 | case 2: return OC2IPC; |
paul@14 | 641 | case 3: return OC3IPC; |
paul@14 | 642 | case 4: return OC4IPC; |
paul@14 | 643 | case 5: return OC5IPC; |
paul@14 | 644 | default: return 0; /* should not occur */ |
paul@14 | 645 | } |
paul@14 | 646 | } |
paul@14 | 647 | |
paul@14 | 648 | /* Return the output compare interrupt flags for combining with a register. */ |
paul@14 | 649 | |
paul@14 | 650 | int OC_INT_FLAGS(int unit, uint8_t flags) |
paul@14 | 651 | { |
paul@14 | 652 | return (flags & 0b1) << (OCINTBASE + (unit - OCMIN) * OCINTSTEP); |
paul@14 | 653 | } |
paul@14 | 654 | |
paul@32 | 655 | /* Return encoded parallel mode interrupt priorities for combining with a register. */ |
paul@32 | 656 | |
paul@32 | 657 | uint32_t PM_IPC_PRI(int port, uint8_t pri, uint8_t sub) |
paul@32 | 658 | { |
paul@32 | 659 | (void) port; |
paul@32 | 660 | return PRI(pri, sub) << PMIPCBASE; |
paul@32 | 661 | } |
paul@32 | 662 | |
paul@32 | 663 | /* Return the parallel mode interrupt priorities register. */ |
paul@32 | 664 | |
paul@32 | 665 | uint32_t PM_IPC_REG(int port) |
paul@32 | 666 | { |
paul@32 | 667 | (void) port; |
paul@32 | 668 | return PMIPC; |
paul@32 | 669 | } |
paul@32 | 670 | |
paul@32 | 671 | /* Return the parallel mode interrupt flags for combining with a register. */ |
paul@32 | 672 | |
paul@32 | 673 | int PM_INT_FLAGS(int port, uint8_t flags) |
paul@32 | 674 | { |
paul@32 | 675 | return (flags & 0b11) << (PMINTBASE + (port - PMMIN) * PMINTSTEP); |
paul@32 | 676 | } |
paul@32 | 677 | |
paul@7 | 678 | /* Return encoded timer interrupt priorities for combining with a register. */ |
paul@7 | 679 | |
paul@7 | 680 | uint32_t TIMER_IPC_PRI(int timer, uint8_t pri, uint8_t sub) |
paul@7 | 681 | { |
paul@7 | 682 | (void) timer; |
paul@7 | 683 | return PRI(pri, sub) << TIMERIPCBASE; |
paul@7 | 684 | } |
paul@7 | 685 | |
paul@7 | 686 | /* Return the timer interrupt priorities register. */ |
paul@7 | 687 | |
paul@7 | 688 | uint32_t TIMER_IPC_REG(int timer) |
paul@7 | 689 | { |
paul@7 | 690 | switch (timer) |
paul@7 | 691 | { |
paul@7 | 692 | case 1: return TIMER1IPC; |
paul@7 | 693 | case 2: return TIMER2IPC; |
paul@7 | 694 | case 3: return TIMER3IPC; |
paul@7 | 695 | case 4: return TIMER4IPC; |
paul@7 | 696 | case 5: return TIMER5IPC; |
paul@7 | 697 | default: return 0; /* should not occur */ |
paul@7 | 698 | } |
paul@7 | 699 | } |
paul@7 | 700 | |
paul@7 | 701 | /* Return the timer interrupt flags for combining with a register. */ |
paul@7 | 702 | |
paul@7 | 703 | int TIMER_INT_FLAGS(int timer, uint8_t flags) |
paul@7 | 704 | { |
paul@7 | 705 | return (flags & 0b1) << (TIMERINTBASE + (timer - TIMERMIN) * TIMERINTSTEP); |
paul@7 | 706 | } |
paul@7 | 707 | |
paul@3 | 708 | /* Return encoded UART interrupt priorities for combining with a register. */ |
paul@3 | 709 | |
paul@7 | 710 | uint32_t UART_IPC_PRI(int uart, uint8_t pri, uint8_t sub) |
paul@3 | 711 | { |
paul@7 | 712 | return PRI(pri, sub) << (uart == 1 ? UART1IPCBASE : UART2IPCBASE); |
paul@3 | 713 | } |
paul@3 | 714 | |
paul@3 | 715 | /* Return the UART interrupt priorities register. */ |
paul@3 | 716 | |
paul@7 | 717 | uint32_t UART_IPC_REG(int uart) |
paul@3 | 718 | { |
paul@7 | 719 | return uart == 1 ? UART1IPC : UART2IPC; |
paul@3 | 720 | } |
paul@3 | 721 | |
paul@7 | 722 | /* Return the UART interrupt flags for combining with a register. */ |
paul@3 | 723 | |
paul@7 | 724 | int UART_INT_FLAGS(int uart, uint8_t flags) |
paul@3 | 725 | { |
paul@7 | 726 | return (flags & 0b111) << (UARTINTBASE + (uart - UARTMIN) * UARTINTSTEP); |
paul@3 | 727 | } |