paul@148 | 1 | = VGA Output Example (Dual-Channel DMA Transfers) = |
paul@148 | 2 | |
paul@148 | 3 | This example demonstrates the generation of an analogue VGA signal from a |
paul@148 | 4 | PIC32 microcontroller using general output pins. It follows on from the work |
paul@148 | 5 | done in the VGAPIC32 project. The result is not entirely satisfactory: |
paul@148 | 6 | |
paul@148 | 7 | * Every fourth pixel is wider than the others, this apparently being an |
paul@148 | 8 | artefact of the DMA transfer mechanism. |
paul@148 | 9 | |
paul@148 | 10 | It might be possible to introduce some kind of delay and even out the pixel |
paul@148 | 11 | widths, but this has not been investigated with hardware. However, unlike the |
paul@148 | 12 | [[../vga-pmp|vga-pmp]] example, there is no accompanying signal to potentially |
paul@148 | 13 | orchestrate the staging of individual pixels at a slightly delayed rate. |
paul@148 | 14 | Potentially, the peripheral clock signal might be generated and processed to |
paul@148 | 15 | make such a signal. |
paul@148 | 16 | |
paul@148 | 17 | Unlike the [[../vga|vga]] example, this example employs two DMA channels for |
paul@148 | 18 | pixel data which are interleaved to investigate a potential remedy for the |
paul@148 | 19 | wide pixel effect. Unfortunately, despite each channel contributing every |
paul@148 | 20 | other word (or group of four pixels), the effect persists. However, the |
paul@148 | 21 | picture is perhaps more stable than in the [[../vga|vga]] example. |
paul@148 | 22 | |
paul@148 | 23 | One significant problem with this example is that scrolling causes the DMA |
paul@148 | 24 | channels to become ordered incorrectly. This does not affect the |
paul@148 | 25 | [[../vga-timer|vga-timer]] example which also employs two DMA channels. |
paul@148 | 26 | |
paul@148 | 27 | == Hardware Details == |
paul@148 | 28 | |
paul@148 | 29 | The pin usage of this solution is documented below. |
paul@148 | 30 | |
paul@148 | 31 | === PIC32MX270F256B-50I/SP Pin Assignments === |
paul@148 | 32 | |
paul@148 | 33 | {{{ |
paul@148 | 34 | MCLR# 1 \/ 28 |
paul@148 | 35 | HSYNC/OC1/RA0 2 27 |
paul@148 | 36 | VSYNC/OC2/RA1 3 26 RB15/U1TX |
paul@148 | 37 | D0/RB0 4 25 RB14 |
paul@148 | 38 | D1/RB1 5 24 RB13/U1RX |
paul@148 | 39 | D2/RB2 6 23 |
paul@148 | 40 | D3/RB3 7 22 RB11/PGEC2 |
paul@148 | 41 | 8 21 RB10/PGEC3 |
paul@148 | 42 | RA2 9 20 |
paul@148 | 43 | RA3 10 19 |
paul@148 | 44 | D4/RB4 11 18 RB9 |
paul@148 | 45 | 12 17 RB8 |
paul@148 | 46 | 13 16 RB7/D7 |
paul@148 | 47 | D5/RB5 14 15 |
paul@148 | 48 | }}} |
paul@148 | 49 | |
paul@148 | 50 | Note that RB6 is not available on pin 15 on this device (it is needed for VBUS |
paul@148 | 51 | unlike the MX170 variant). |
paul@148 | 52 | |
paul@148 | 53 | === UART Connections === |
paul@148 | 54 | |
paul@148 | 55 | UART1 is exposed by the RB13 and RB15 pins. |
paul@148 | 56 | |
paul@148 | 57 | === Data Signal Routing === |
paul@148 | 58 | |
paul@148 | 59 | For one bit of intensity, two bits per colour channel: |
paul@148 | 60 | |
paul@148 | 61 | {{{ |
paul@148 | 62 | D7 -> 2200R -> I |
paul@148 | 63 | |
paul@148 | 64 | I -> diode -> R |
paul@148 | 65 | I -> diode -> G |
paul@148 | 66 | I -> diode -> B |
paul@148 | 67 | |
paul@148 | 68 | D6 (not connected) |
paul@148 | 69 | |
paul@148 | 70 | D5 -> 470R -> R |
paul@148 | 71 | D4 -> 1000R -> R |
paul@148 | 72 | D3 -> 470R -> G |
paul@148 | 73 | D2 -> 1000R -> G |
paul@148 | 74 | D1 -> 470R -> B |
paul@148 | 75 | D0 -> 1000R -> B |
paul@148 | 76 | |
paul@148 | 77 | HSYNC -> HS |
paul@148 | 78 | VSYNC -> VS |
paul@148 | 79 | }}} |
paul@148 | 80 | |
paul@148 | 81 | === Output Socket Pinout === |
paul@148 | 82 | |
paul@148 | 83 | {{{ |
paul@148 | 84 | 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) |
paul@148 | 85 | |
paul@148 | 86 | 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) |
paul@148 | 87 | |
paul@148 | 88 | 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) |
paul@148 | 89 | }}} |
paul@148 | 90 | |
paul@148 | 91 | === Output Cable Pinout === |
paul@148 | 92 | |
paul@148 | 93 | {{{ |
paul@148 | 94 | 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) |
paul@148 | 95 | |
paul@148 | 96 | 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) |
paul@148 | 97 | |
paul@148 | 98 | 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) |
paul@148 | 99 | }}} |
paul@148 | 100 | |
paul@148 | 101 | == References == |
paul@148 | 102 | |
paul@148 | 103 | https://en.wikipedia.org/wiki/VGA_connector |
paul@148 | 104 | |
paul@148 | 105 | http://papilio.cc/index.php?n=Papilio.VGAWing |
paul@148 | 106 | |
paul@148 | 107 | http://lucidscience.com/pro-vga%20video%20generator-2.aspx |
paul@148 | 108 | |
paul@148 | 109 | https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga |