paul@24 | 1 | /* |
paul@24 | 2 | * Generate a VGA signal using a PIC32 microcontroller. |
paul@24 | 3 | * |
paul@24 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@24 | 5 | * |
paul@24 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@24 | 7 | * it under the terms of the GNU General Public License as published by |
paul@24 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@24 | 9 | * (at your option) any later version. |
paul@24 | 10 | * |
paul@24 | 11 | * This program is distributed in the hope that it will be useful, |
paul@24 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@24 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@24 | 14 | * GNU General Public License for more details. |
paul@24 | 15 | * |
paul@24 | 16 | * You should have received a copy of the GNU General Public License |
paul@24 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@24 | 18 | */ |
paul@24 | 19 | |
paul@24 | 20 | |
paul@24 | 21 | #include "pic32_c.h" |
paul@24 | 22 | #include "init.h" |
paul@24 | 23 | #include "debug.h" |
paul@24 | 24 | #include "main.h" |
paul@24 | 25 | #include "vga.h" |
paul@24 | 26 | |
paul@24 | 27 | |
paul@24 | 28 | |
paul@24 | 29 | /* Display state. */ |
paul@24 | 30 | |
paul@24 | 31 | static void (*state_handler)(void); |
paul@24 | 32 | static uint32_t line; |
paul@24 | 33 | |
paul@24 | 34 | /* Pixel data. */ |
paul@24 | 35 | |
paul@24 | 36 | static uint8_t linedata[LINE_LENGTH]; |
paul@24 | 37 | static const uint8_t zerodata[ZERO_LENGTH] = {0}; |
paul@24 | 38 | |
paul@24 | 39 | |
paul@24 | 40 | |
paul@24 | 41 | static void test_linedata(void) |
paul@24 | 42 | { |
paul@24 | 43 | int i; |
paul@24 | 44 | |
paul@24 | 45 | for (i = 0; i < LINE_LENGTH; i++) |
paul@24 | 46 | linedata[i] = (i % 2) ? 0xff : 0x00; |
paul@24 | 47 | } |
paul@24 | 48 | |
paul@24 | 49 | /* Blink an attached LED with delays implemented using a loop. */ |
paul@24 | 50 | |
paul@24 | 51 | static void blink(uint32_t delay, uint32_t port, uint32_t pins) |
paul@24 | 52 | { |
paul@24 | 53 | uint32_t counter; |
paul@24 | 54 | |
paul@24 | 55 | /* Clear outputs (LED). */ |
paul@24 | 56 | |
paul@24 | 57 | CLR_REG(port, pins); |
paul@24 | 58 | |
paul@24 | 59 | while (1) |
paul@24 | 60 | { |
paul@24 | 61 | counter = delay; |
paul@24 | 62 | |
paul@24 | 63 | while (counter--) __asm__(""); /* retain loop */ |
paul@24 | 64 | |
paul@24 | 65 | /* Invert outputs (LED). */ |
paul@24 | 66 | |
paul@24 | 67 | INV_REG(port, pins); |
paul@24 | 68 | } |
paul@24 | 69 | } |
paul@24 | 70 | |
paul@24 | 71 | |
paul@24 | 72 | |
paul@24 | 73 | /* Main program. */ |
paul@24 | 74 | |
paul@24 | 75 | void main(void) |
paul@24 | 76 | { |
paul@24 | 77 | line = 0; |
paul@24 | 78 | state_handler = vbp_active; |
paul@24 | 79 | test_linedata(); |
paul@24 | 80 | |
paul@24 | 81 | init_memory(); |
paul@24 | 82 | init_pins(); |
paul@24 | 83 | init_outputs(); |
paul@24 | 84 | |
paul@24 | 85 | unlock_config(); |
paul@24 | 86 | config_oc(); |
paul@24 | 87 | config_uart(); |
paul@24 | 88 | lock_config(); |
paul@24 | 89 | |
paul@24 | 90 | init_dma(); |
paul@24 | 91 | |
paul@24 | 92 | /* Initiate DMA on the Timer2 interrupt transferring line data to the first |
paul@24 | 93 | byte of PORTB. Do not enable the channel for initiation until the visible |
paul@24 | 94 | region is about to start. */ |
paul@24 | 95 | |
paul@24 | 96 | dma_init(0, 3); |
paul@24 | 97 | dma_set_auto_enable(0, 1); |
paul@24 | 98 | dma_set_interrupt(0, T2, 1); |
paul@24 | 99 | dma_set_transfer(0, PHYSICAL((uint32_t) linedata), LINE_LENGTH, |
paul@24 | 100 | HW_PHYSICAL(PORTB), 1, |
paul@24 | 101 | LINE_LENGTH); |
paul@24 | 102 | dma_init_interrupt(0, 0b00001000, 1, 3); |
paul@24 | 103 | |
paul@24 | 104 | /* Enable DMA on the preceding channel's completion, with this also |
paul@24 | 105 | initiating transfers. */ |
paul@24 | 106 | |
paul@24 | 107 | dma_init(1, 3); |
paul@24 | 108 | dma_set_chaining(1, dma_chain_previous); |
paul@24 | 109 | dma_set_interrupt(1, DMA0, 1); |
paul@24 | 110 | dma_set_transfer(1, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH, |
paul@24 | 111 | HW_PHYSICAL(PORTB), 1, |
paul@24 | 112 | ZERO_LENGTH); |
paul@24 | 113 | dma_set_receive_events(1, 1); |
paul@24 | 114 | |
paul@24 | 115 | /* Configure a timer for the horizontal sync. The timer has no prescaling |
paul@24 | 116 | (0). */ |
paul@24 | 117 | |
paul@24 | 118 | timer_init(2, 0, HFREQ_LIMIT); |
paul@24 | 119 | timer_on(2); |
paul@24 | 120 | |
paul@24 | 121 | /* Horizontal sync. */ |
paul@24 | 122 | |
paul@24 | 123 | /* Configure output compare in dual compare (continuous output) mode using |
paul@24 | 124 | Timer2 as time base. The interrupt condition drives the first DMA channel |
paul@27 | 125 | and is handled to drive the display state machine. */ |
paul@24 | 126 | |
paul@24 | 127 | oc_init(1, 0b101, 2); |
paul@24 | 128 | oc_set_pulse(1, HSYNC_END); |
paul@24 | 129 | oc_set_pulse_end(1, HSYNC_START); |
paul@24 | 130 | oc_init_interrupt(1, 7, 3); |
paul@24 | 131 | oc_on(1); |
paul@24 | 132 | |
paul@24 | 133 | /* Vertical sync. */ |
paul@24 | 134 | |
paul@24 | 135 | /* Configure output compare in single compare (output driven low) mode using |
paul@24 | 136 | Timer2 as time base. The unit is enabled later. It is only really used to |
paul@24 | 137 | achieve precisely-timed level transitions in hardware. */ |
paul@24 | 138 | |
paul@24 | 139 | oc_init(2, 0b010, 2); |
paul@24 | 140 | oc_set_pulse(2, 0); |
paul@24 | 141 | |
paul@24 | 142 | uart_init(1, 115200); |
paul@24 | 143 | uart_on(1); |
paul@24 | 144 | |
paul@24 | 145 | interrupts_on(); |
paul@24 | 146 | |
paul@24 | 147 | blink(3 << 24, PORTA, 1 << 3); |
paul@24 | 148 | } |
paul@24 | 149 | |
paul@24 | 150 | |
paul@24 | 151 | |
paul@24 | 152 | /* Exception and interrupt handlers. */ |
paul@24 | 153 | |
paul@24 | 154 | void exception_handler(void) |
paul@24 | 155 | { |
paul@24 | 156 | blink(3 << 12, PORTA, 1 << 3); |
paul@24 | 157 | } |
paul@24 | 158 | |
paul@24 | 159 | void interrupt_handler(void) |
paul@24 | 160 | { |
paul@24 | 161 | uint32_t ifs; |
paul@24 | 162 | |
paul@24 | 163 | /* Check for a OC1 interrupt condition. */ |
paul@24 | 164 | |
paul@24 | 165 | ifs = REG(OCIFS) & OC_INT_FLAGS(1, OCxIF); |
paul@24 | 166 | |
paul@24 | 167 | if (ifs) |
paul@24 | 168 | { |
paul@24 | 169 | line += 1; |
paul@24 | 170 | state_handler(); |
paul@24 | 171 | CLR_REG(OCIFS, ifs); |
paul@24 | 172 | } |
paul@24 | 173 | } |
paul@24 | 174 | |
paul@24 | 175 | |
paul@24 | 176 | |
paul@24 | 177 | /* Vertical back porch region. */ |
paul@24 | 178 | |
paul@24 | 179 | void vbp_active(void) |
paul@24 | 180 | { |
paul@24 | 181 | if (line < VISIBLE_START) |
paul@24 | 182 | return; |
paul@24 | 183 | |
paul@24 | 184 | /* Enter the visible region. */ |
paul@24 | 185 | |
paul@24 | 186 | state_handler = visible_active; |
paul@24 | 187 | |
paul@24 | 188 | /* NOTE: Set the line address. */ |
paul@24 | 189 | |
paul@24 | 190 | /* Enable the channel for the next line. */ |
paul@24 | 191 | |
paul@24 | 192 | dma_on(0); |
paul@24 | 193 | } |
paul@24 | 194 | |
paul@24 | 195 | /* Visible region. */ |
paul@24 | 196 | |
paul@24 | 197 | void visible_active(void) |
paul@24 | 198 | { |
paul@24 | 199 | uint32_t ifs; |
paul@24 | 200 | |
paul@24 | 201 | /* Remove any DMA interrupt condition (CHBCIF). */ |
paul@24 | 202 | |
paul@24 | 203 | ifs = REG(DMAIFS) & DMA_INT_FLAGS(0, DCHxIF); |
paul@24 | 204 | |
paul@24 | 205 | if (ifs) |
paul@24 | 206 | { |
paul@24 | 207 | CLR_REG(DMA_REG(0, DCHxINT), 0b11111111); |
paul@24 | 208 | CLR_REG(DMAIFS, ifs); |
paul@24 | 209 | INV_REG(PORTA, 1 << 2); |
paul@24 | 210 | } |
paul@24 | 211 | |
paul@24 | 212 | if (line < VFP_START) |
paul@24 | 213 | { |
paul@24 | 214 | /* NOTE: Update the line address and handle wraparound. */ |
paul@24 | 215 | |
paul@24 | 216 | return; |
paul@24 | 217 | } |
paul@24 | 218 | |
paul@24 | 219 | /* End the visible region. */ |
paul@24 | 220 | |
paul@24 | 221 | state_handler = vfp_active; |
paul@24 | 222 | |
paul@24 | 223 | /* Disable the channel for the next line. */ |
paul@24 | 224 | |
paul@24 | 225 | dma_off(0); |
paul@24 | 226 | } |
paul@24 | 227 | |
paul@24 | 228 | /* Vertical front porch region. */ |
paul@24 | 229 | |
paul@24 | 230 | void vfp_active(void) |
paul@24 | 231 | { |
paul@24 | 232 | if (line < VSYNC_START) |
paul@24 | 233 | return; |
paul@24 | 234 | |
paul@24 | 235 | /* Enter the vertical sync region. */ |
paul@24 | 236 | |
paul@24 | 237 | state_handler = vsync_active; |
paul@24 | 238 | |
paul@24 | 239 | /* Bring vsync low (single compare, output driven low) when the next line |
paul@24 | 240 | starts. */ |
paul@24 | 241 | |
paul@24 | 242 | oc_init(2, 0b010, 2); |
paul@24 | 243 | oc_on(2); |
paul@24 | 244 | } |
paul@24 | 245 | |
paul@24 | 246 | /* Vertical sync region. */ |
paul@24 | 247 | |
paul@24 | 248 | void vsync_active(void) |
paul@24 | 249 | { |
paul@24 | 250 | if (line < VSYNC_END) |
paul@24 | 251 | return; |
paul@24 | 252 | |
paul@24 | 253 | /* Start again at the top of the display. */ |
paul@24 | 254 | |
paul@24 | 255 | line = 0; |
paul@24 | 256 | state_handler = vbp_active; |
paul@24 | 257 | |
paul@24 | 258 | /* Bring vsync high (single compare, output driven high) when the next line |
paul@24 | 259 | starts. */ |
paul@24 | 260 | |
paul@24 | 261 | oc_init(2, 0b001, 2); |
paul@24 | 262 | oc_on(2); |
paul@24 | 263 | } |
paul@24 | 264 | |
paul@24 | 265 | |
paul@24 | 266 | |
paul@24 | 267 | /* Peripheral pin configuration. */ |
paul@24 | 268 | |
paul@24 | 269 | void config_oc(void) |
paul@24 | 270 | { |
paul@24 | 271 | /* Map OC1 to RPA0. */ |
paul@24 | 272 | |
paul@24 | 273 | REG(RPA0R) = 0b0101; /* RPA0R<3:0> = 0101 (OC1) */ |
paul@24 | 274 | |
paul@24 | 275 | /* Map OC2 to RPA1. */ |
paul@24 | 276 | |
paul@24 | 277 | REG(RPA1R) = 0b0101; /* RPA1R<3:0> = 0101 (OC2) */ |
paul@24 | 278 | } |
paul@24 | 279 | |
paul@24 | 280 | void config_uart(void) |
paul@24 | 281 | { |
paul@24 | 282 | /* Map U1RX to RPB13. */ |
paul@24 | 283 | |
paul@24 | 284 | REG(U1RXR) = 0b0011; /* U1RXR<3:0> = 0011 (RPB13) */ |
paul@24 | 285 | |
paul@24 | 286 | /* Map U1TX to RPB15. */ |
paul@24 | 287 | |
paul@24 | 288 | REG(RPB15R) = 0b0001; /* RPB15R<3:0> = 0001 (U1TX) */ |
paul@24 | 289 | |
paul@24 | 290 | /* Set RPB13 to input. */ |
paul@24 | 291 | |
paul@24 | 292 | SET_REG(TRISB, 1 << 13); |
paul@24 | 293 | } |