paul@15 | 1 | /* |
paul@15 | 2 | * PIC32 peripheral configuration and initialisation. |
paul@15 | 3 | * |
paul@15 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@15 | 5 | * |
paul@15 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@15 | 7 | * it under the terms of the GNU General Public License as published by |
paul@15 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@15 | 9 | * (at your option) any later version. |
paul@15 | 10 | * |
paul@15 | 11 | * This program is distributed in the hope that it will be useful, |
paul@15 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@15 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@15 | 14 | * GNU General Public License for more details. |
paul@15 | 15 | * |
paul@15 | 16 | * You should have received a copy of the GNU General Public License |
paul@15 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@15 | 18 | */ |
paul@15 | 19 | |
paul@0 | 20 | #include "cpu.h" |
paul@0 | 21 | #include "pic32_c.h" |
paul@3 | 22 | #include "init.h" |
paul@0 | 23 | |
paul@0 | 24 | |
paul@0 | 25 | |
paul@0 | 26 | /* Basic memory and pin initialisation. */ |
paul@0 | 27 | |
paul@0 | 28 | void init_memory(void) |
paul@0 | 29 | { |
paul@0 | 30 | /* |
paul@0 | 31 | Configure RAM. |
paul@0 | 32 | See: http://microchipdeveloper.com/32bit:mx-arch-exceptions-processor-initialization |
paul@0 | 33 | */ |
paul@0 | 34 | |
paul@0 | 35 | uint32_t config = REG(BMXCON); |
paul@0 | 36 | |
paul@0 | 37 | /* Set zero wait states for address setup. */ |
paul@0 | 38 | |
paul@0 | 39 | config &= ~(1 << 6); /* BMXCON<6> = BMXWSDRM = 0 */ |
paul@0 | 40 | |
paul@0 | 41 | /* Set bus arbitration mode. */ |
paul@0 | 42 | |
paul@0 | 43 | config &= ~0b111; |
paul@0 | 44 | config |= 0b010; /* BMXCON<2:0> = BMXARB<2:0> = 2 */ |
paul@0 | 45 | |
paul@0 | 46 | REG(BMXCON) = config; |
paul@0 | 47 | } |
paul@0 | 48 | |
paul@0 | 49 | void init_pins(void) |
paul@0 | 50 | { |
paul@0 | 51 | /* DEVCFG0<2> also needs setting to 0 before the program is run. */ |
paul@0 | 52 | |
paul@0 | 53 | CLR_REG(CFGCON, 1 << 3); /* CFGCON<3> = JTAGEN = 0 */ |
paul@0 | 54 | } |
paul@0 | 55 | |
paul@0 | 56 | void init_outputs(void) |
paul@0 | 57 | { |
paul@0 | 58 | /* Remove analogue features from pins. */ |
paul@0 | 59 | |
paul@0 | 60 | REG(ANSELA) = 0; |
paul@0 | 61 | REG(ANSELB) = 0; |
paul@0 | 62 | |
paul@3 | 63 | /* Set pins as outputs. */ |
paul@3 | 64 | |
paul@0 | 65 | REG(TRISA) = 0; |
paul@0 | 66 | REG(TRISB) = 0; |
paul@0 | 67 | |
paul@3 | 68 | /* Clear outputs. */ |
paul@3 | 69 | |
paul@0 | 70 | REG(PORTA) = 0; |
paul@0 | 71 | REG(PORTB) = 0; |
paul@0 | 72 | } |
paul@0 | 73 | |
paul@0 | 74 | |
paul@0 | 75 | |
paul@0 | 76 | /* Peripheral pin configuration. */ |
paul@0 | 77 | |
paul@0 | 78 | void config_uart(void) |
paul@0 | 79 | { |
paul@3 | 80 | /* NOTE: Configuring UART1 for specific pins. */ |
paul@3 | 81 | |
paul@0 | 82 | /* Map U1RX to RPB13. */ |
paul@0 | 83 | |
paul@0 | 84 | REG(U1RXR) = 0b0011; /* U1RXR<3:0> = 0011 (RPB13) */ |
paul@0 | 85 | |
paul@0 | 86 | /* Map U1TX to RPB15. */ |
paul@0 | 87 | |
paul@0 | 88 | REG(RPB15R) = 0b0001; /* RPB15R<3:0> = 0001 (U1TX) */ |
paul@0 | 89 | |
paul@0 | 90 | /* Set RPB13 to input. */ |
paul@0 | 91 | |
paul@0 | 92 | SET_REG(TRISB, 1 << 13); |
paul@0 | 93 | } |
paul@0 | 94 | |
paul@0 | 95 | void lock_config(void) |
paul@0 | 96 | { |
paul@0 | 97 | SET_REG(CFGCON, 1 << 13); /* IOLOCK = 1 */ |
paul@0 | 98 | |
paul@0 | 99 | /* Lock the configuration again. */ |
paul@0 | 100 | |
paul@0 | 101 | REG(SYSKEY) = 0x33333333; |
paul@0 | 102 | } |
paul@0 | 103 | |
paul@0 | 104 | void unlock_config(void) |
paul@0 | 105 | { |
paul@0 | 106 | /* Unlock the configuration register bits. */ |
paul@0 | 107 | |
paul@0 | 108 | REG(SYSKEY) = 0; |
paul@0 | 109 | REG(SYSKEY) = 0xAA996655; |
paul@0 | 110 | REG(SYSKEY) = 0x556699AA; |
paul@0 | 111 | |
paul@0 | 112 | CLR_REG(CFGCON, 1 << 13); /* IOLOCK = 0 */ |
paul@0 | 113 | } |
paul@0 | 114 | |
paul@0 | 115 | |
paul@0 | 116 | |
paul@0 | 117 | /* Convenience operations. */ |
paul@0 | 118 | |
paul@0 | 119 | void interrupts_on(void) |
paul@0 | 120 | { |
paul@0 | 121 | init_interrupts(); |
paul@0 | 122 | enable_interrupts(); |
paul@0 | 123 | handle_error_level(); |
paul@0 | 124 | } |
paul@0 | 125 | |
paul@0 | 126 | |
paul@0 | 127 | |
paul@3 | 128 | /* DMA configuration. */ |
paul@3 | 129 | |
paul@3 | 130 | void init_dma(void) |
paul@3 | 131 | { |
paul@3 | 132 | /* Disable DMA interrupts. */ |
paul@3 | 133 | |
paul@3 | 134 | CLR_REG(DMAIEC, 0b1111 << DMAINTBASE); /* DMA3IE...DMA0IE = 0 */ |
paul@3 | 135 | |
paul@3 | 136 | /* Clear DMA interrupt flags. */ |
paul@3 | 137 | |
paul@3 | 138 | CLR_REG(DMAIFS, 0b1111 << DMAINTBASE); /* DMA3IF...DMA0IF = 0 */ |
paul@3 | 139 | |
paul@3 | 140 | /* Enable DMA. */ |
paul@3 | 141 | |
paul@3 | 142 | SET_REG(DMACON, 1 << 15); |
paul@3 | 143 | } |
paul@3 | 144 | |
paul@3 | 145 | /* Initialise the given channel. */ |
paul@0 | 146 | |
paul@10 | 147 | void dma_init(int channel, uint8_t pri) |
paul@0 | 148 | { |
paul@7 | 149 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@3 | 150 | return; |
paul@3 | 151 | |
paul@3 | 152 | /* Initialise a channel. */ |
paul@3 | 153 | |
paul@10 | 154 | REG(DMA_REG(channel, DCHxCON)) = pri & 0b11; |
paul@3 | 155 | REG(DMA_REG(channel, DCHxECON)) = 0; |
paul@3 | 156 | REG(DMA_REG(channel, DCHxINT)) = 0; |
paul@3 | 157 | } |
paul@3 | 158 | |
paul@10 | 159 | /* Set the channel auto-enable mode. */ |
paul@10 | 160 | |
paul@10 | 161 | void dma_set_auto_enable(int channel, int auto_enable) |
paul@10 | 162 | { |
paul@10 | 163 | (auto_enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 4); |
paul@10 | 164 | } |
paul@10 | 165 | |
paul@10 | 166 | /* Set the channel chaining mode. */ |
paul@10 | 167 | |
paul@10 | 168 | void dma_set_chaining(int channel, enum dma_chain chain) |
paul@10 | 169 | { |
paul@10 | 170 | (chain != dma_chain_none ? |
paul@10 | 171 | SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 5); |
paul@10 | 172 | |
paul@10 | 173 | (chain == dma_chain_next ? |
paul@10 | 174 | SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 8); |
paul@10 | 175 | } |
paul@10 | 176 | |
paul@3 | 177 | /* Configure a channel's initiation interrupt. */ |
paul@3 | 178 | |
paul@3 | 179 | void dma_set_interrupt(int channel, uint8_t int_num, int enable) |
paul@3 | 180 | { |
paul@7 | 181 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@3 | 182 | return; |
paul@0 | 183 | |
paul@3 | 184 | /* Allow an interrupt to trigger the transfer. */ |
paul@3 | 185 | |
paul@3 | 186 | REG(DMA_REG(channel, DCHxECON)) = (int_num << 8) | |
paul@3 | 187 | ((enable ? 1 : 0) << 4); |
paul@3 | 188 | } |
paul@3 | 189 | |
paul@3 | 190 | /* Set a channel's transfer parameters. */ |
paul@3 | 191 | |
paul@3 | 192 | void dma_set_transfer(int channel, |
paul@3 | 193 | uint32_t source_start_address, uint16_t source_size, |
paul@3 | 194 | uint32_t destination_start_address, uint16_t destination_size, |
paul@3 | 195 | uint16_t cell_size) |
paul@3 | 196 | { |
paul@7 | 197 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@3 | 198 | return; |
paul@0 | 199 | |
paul@3 | 200 | REG(DMA_REG(channel, DCHxSSIZ)) = source_size; |
paul@3 | 201 | REG(DMA_REG(channel, DCHxSSA)) = source_start_address; |
paul@3 | 202 | REG(DMA_REG(channel, DCHxDSIZ)) = destination_size; |
paul@3 | 203 | REG(DMA_REG(channel, DCHxDSA)) = destination_start_address; |
paul@3 | 204 | REG(DMA_REG(channel, DCHxCSIZ)) = cell_size; |
paul@3 | 205 | } |
paul@3 | 206 | |
paul@3 | 207 | /* Configure interrupts caused by the channel. */ |
paul@0 | 208 | |
paul@3 | 209 | void dma_init_interrupt(int channel, uint8_t conditions, |
paul@7 | 210 | uint8_t pri, uint8_t sub) |
paul@3 | 211 | { |
paul@7 | 212 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@3 | 213 | return; |
paul@0 | 214 | |
paul@10 | 215 | /* Disable channel interrupt and clear interrupt flag. */ |
paul@10 | 216 | |
paul@10 | 217 | CLR_REG(DMAIEC, DMA_INT_FLAGS(channel, 1)); |
paul@10 | 218 | CLR_REG(DMAIFS, DMA_INT_FLAGS(channel, 1)); |
paul@10 | 219 | |
paul@3 | 220 | /* Produce an interrupt for the provided conditions. */ |
paul@3 | 221 | |
paul@3 | 222 | REG(DMA_REG(channel, DCHxINT)) = conditions << 16; |
paul@3 | 223 | |
paul@3 | 224 | /* Set interrupt priorities. */ |
paul@3 | 225 | |
paul@14 | 226 | REG(DMAIPC) = (REG(DMAIPC) & |
paul@14 | 227 | ~(DMA_IPC_PRI(channel, 7, 3))) | |
paul@7 | 228 | DMA_IPC_PRI(channel, pri, sub); |
paul@0 | 229 | |
paul@0 | 230 | /* Enable interrupt. */ |
paul@0 | 231 | |
paul@10 | 232 | SET_REG(DMAIEC, DMA_INT_FLAGS(channel, 1)); |
paul@3 | 233 | } |
paul@3 | 234 | |
paul@3 | 235 | /* Enable a DMA channel. */ |
paul@3 | 236 | |
paul@3 | 237 | void dma_on(int channel) |
paul@3 | 238 | { |
paul@7 | 239 | if ((channel < DCHMIN) || (channel > DCHMAX)) |
paul@3 | 240 | return; |
paul@3 | 241 | |
paul@3 | 242 | /* Enable channel. */ |
paul@3 | 243 | |
paul@3 | 244 | SET_REG(DMA_REG(channel, DCHxCON), 1 << 7); |
paul@3 | 245 | } |
paul@3 | 246 | |
paul@7 | 247 | |
paul@7 | 248 | |
paul@14 | 249 | /* Output compare configuration. */ |
paul@14 | 250 | |
paul@14 | 251 | void oc_init(int unit, uint8_t mode, int timer) |
paul@14 | 252 | { |
paul@14 | 253 | if ((unit < OCMIN) || (unit > OCMAX)) |
paul@14 | 254 | return; |
paul@14 | 255 | |
paul@14 | 256 | REG(OC_REG(unit, OCxCON)) = (timer == 3 ? (1 << 3) : 0) | (mode & 0b111); |
paul@14 | 257 | } |
paul@14 | 258 | |
paul@14 | 259 | /* Set the start value for the pulse. */ |
paul@14 | 260 | |
paul@14 | 261 | void oc_set_pulse(int unit, uint32_t start) |
paul@14 | 262 | { |
paul@14 | 263 | if ((unit < OCMIN) || (unit > OCMAX)) |
paul@14 | 264 | return; |
paul@14 | 265 | |
paul@14 | 266 | REG(OC_REG(unit, OCxR)) = start; |
paul@14 | 267 | } |
paul@14 | 268 | |
paul@14 | 269 | /* Set the end value for the pulse. */ |
paul@14 | 270 | |
paul@14 | 271 | void oc_set_pulse_end(int unit, uint32_t end) |
paul@14 | 272 | { |
paul@14 | 273 | if ((unit < OCMIN) || (unit > OCMAX)) |
paul@14 | 274 | return; |
paul@14 | 275 | |
paul@14 | 276 | REG(OC_REG(unit, OCxRS)) = end; |
paul@14 | 277 | } |
paul@14 | 278 | |
paul@14 | 279 | /* Configure interrupts caused by the unit. */ |
paul@14 | 280 | |
paul@14 | 281 | void oc_init_interrupt(int unit, uint8_t pri, uint8_t sub) |
paul@14 | 282 | { |
paul@14 | 283 | if ((unit < OCMIN) || (unit > OCMAX)) |
paul@14 | 284 | return; |
paul@14 | 285 | |
paul@14 | 286 | /* Disable interrupt and clear interrupt flag. */ |
paul@14 | 287 | |
paul@14 | 288 | CLR_REG(OCIEC, OC_INT_FLAGS(unit, OCxIE)); |
paul@14 | 289 | CLR_REG(OCIFS, OC_INT_FLAGS(unit, OCxIF)); |
paul@14 | 290 | |
paul@14 | 291 | /* Set interrupt priorities. */ |
paul@14 | 292 | |
paul@14 | 293 | REG(OC_IPC_REG(unit)) = (REG(OC_IPC_REG(unit)) & |
paul@14 | 294 | ~(OC_IPC_PRI(unit, 7, 3))) | |
paul@14 | 295 | OC_IPC_PRI(unit, pri, sub); |
paul@14 | 296 | |
paul@14 | 297 | /* Enable interrupt. */ |
paul@14 | 298 | |
paul@14 | 299 | SET_REG(OCIEC, OC_INT_FLAGS(unit, OCxIE)); |
paul@14 | 300 | } |
paul@14 | 301 | |
paul@14 | 302 | /* Enable a unit. */ |
paul@14 | 303 | |
paul@14 | 304 | void oc_on(int unit) |
paul@14 | 305 | { |
paul@14 | 306 | if ((unit < OCMIN) || (unit > OCMAX)) |
paul@14 | 307 | return; |
paul@14 | 308 | |
paul@14 | 309 | SET_REG(OC_REG(unit, OCxCON), 1 << 15); |
paul@14 | 310 | } |
paul@14 | 311 | |
paul@14 | 312 | |
paul@14 | 313 | |
paul@7 | 314 | /* Timer configuration. */ |
paul@7 | 315 | |
paul@7 | 316 | void timer_init(int timer, uint8_t prescale, uint16_t limit) |
paul@7 | 317 | { |
paul@7 | 318 | /* NOTE: Should convert from the real prescale value. */ |
paul@7 | 319 | |
paul@7 | 320 | REG(TIMER_REG(timer, TxCON)) = (prescale & 0b111) << 4; |
paul@7 | 321 | REG(TIMER_REG(timer, TMRx)) = 0; |
paul@7 | 322 | REG(TIMER_REG(timer, PRx)) = limit; |
paul@7 | 323 | } |
paul@7 | 324 | |
paul@7 | 325 | /* Configure interrupts caused by the timer. */ |
paul@7 | 326 | |
paul@7 | 327 | void timer_init_interrupt(int timer, uint8_t pri, uint8_t sub) |
paul@7 | 328 | { |
paul@7 | 329 | if ((timer < TIMERMIN) || (timer > TIMERMAX)) |
paul@7 | 330 | return; |
paul@7 | 331 | |
paul@14 | 332 | /* Disable interrupt and clear interrupt flag. */ |
paul@14 | 333 | |
paul@14 | 334 | CLR_REG(TIMERIEC, TIMER_INT_FLAGS(timer, TxIE)); |
paul@14 | 335 | CLR_REG(TIMERIFS, TIMER_INT_FLAGS(timer, TxIF)); |
paul@14 | 336 | |
paul@7 | 337 | /* Set interrupt priorities. */ |
paul@7 | 338 | |
paul@7 | 339 | REG(TIMER_IPC_REG(timer)) = (REG(TIMER_IPC_REG(timer)) & |
paul@7 | 340 | ~(TIMER_IPC_PRI(timer, 7, 3))) | |
paul@7 | 341 | TIMER_IPC_PRI(timer, pri, sub); |
paul@7 | 342 | |
paul@7 | 343 | /* Enable interrupt. */ |
paul@7 | 344 | |
paul@7 | 345 | SET_REG(TIMERIEC, TIMER_INT_FLAGS(timer, TxIE)); |
paul@7 | 346 | } |
paul@7 | 347 | |
paul@7 | 348 | /* Enable a timer. */ |
paul@7 | 349 | |
paul@7 | 350 | void timer_on(int timer) |
paul@7 | 351 | { |
paul@7 | 352 | if ((timer < TIMERMIN) || (timer > TIMERMAX)) |
paul@7 | 353 | return; |
paul@7 | 354 | |
paul@7 | 355 | SET_REG(TIMER_REG(timer, TxCON), 1 << 15); |
paul@7 | 356 | } |
paul@7 | 357 | |
paul@7 | 358 | |
paul@7 | 359 | |
paul@3 | 360 | /* UART configuration. */ |
paul@3 | 361 | |
paul@7 | 362 | void uart_init(int uart, uint32_t baudrate) |
paul@3 | 363 | { |
paul@3 | 364 | /* NOTE: Configured in the initial payload. */ |
paul@3 | 365 | |
paul@3 | 366 | uint32_t FPB = 24000000; |
paul@3 | 367 | |
paul@7 | 368 | if ((uart < UARTMIN) || (uart > UARTMAX)) |
paul@3 | 369 | return; |
paul@3 | 370 | |
paul@3 | 371 | /* Disable the UART (ON). */ |
paul@3 | 372 | |
paul@7 | 373 | CLR_REG(UART_REG(uart, UxMODE), 1 << 15); |
paul@3 | 374 | |
paul@3 | 375 | /* Set the baud rate. For example: |
paul@3 | 376 | |
paul@3 | 377 | UxBRG<15:0> = BRG |
paul@3 | 378 | = (FPB / (16 * baudrate)) - 1 |
paul@3 | 379 | = (24000000 / (16 * 115200)) - 1 |
paul@3 | 380 | = 12 |
paul@3 | 381 | */ |
paul@3 | 382 | |
paul@7 | 383 | REG(UART_REG(uart, UxBRG)) = (FPB / (16 * baudrate)) - 1; |
paul@3 | 384 | } |
paul@3 | 385 | |
paul@3 | 386 | /* Configure interrupts caused by the UART. */ |
paul@3 | 387 | |
paul@7 | 388 | void uart_init_interrupt(int uart, uint8_t conditions, |
paul@7 | 389 | uint8_t pri, uint8_t sub) |
paul@3 | 390 | { |
paul@7 | 391 | if ((uart < UARTMIN) || (uart > UARTMAX)) |
paul@3 | 392 | return; |
paul@3 | 393 | |
paul@14 | 394 | /* Disable interrupts and clear interrupt flags. */ |
paul@14 | 395 | |
paul@14 | 396 | CLR_REG(UARTIEC, UART_INT_FLAGS(uart, UxTIE | UxRIE | UxEIE)); |
paul@14 | 397 | CLR_REG(UARTIFS, UART_INT_FLAGS(uart, UxTIF | UxRIF | UxEIF)); |
paul@14 | 398 | |
paul@3 | 399 | /* Set priorities: UxIP = pri; UxIS = sub */ |
paul@3 | 400 | |
paul@14 | 401 | REG(UART_IPC_REG(uart)) = (REG(UART_IPC_REG(uart)) & |
paul@14 | 402 | ~UART_IPC_PRI(uart, 7, 3)) | |
paul@14 | 403 | UART_IPC_PRI(uart, pri, sub); |
paul@3 | 404 | |
paul@7 | 405 | /* Enable interrupts. */ |
paul@3 | 406 | |
paul@7 | 407 | SET_REG(UARTIEC, UART_INT_FLAGS(uart, conditions)); |
paul@3 | 408 | } |
paul@3 | 409 | |
paul@3 | 410 | /* Enable a UART. */ |
paul@3 | 411 | |
paul@7 | 412 | void uart_on(int uart) |
paul@3 | 413 | { |
paul@7 | 414 | if ((uart < UARTMIN) || (uart > UARTMAX)) |
paul@3 | 415 | return; |
paul@3 | 416 | |
paul@3 | 417 | /* Enable receive (URXEN) and transmit (UTXEN). */ |
paul@3 | 418 | |
paul@7 | 419 | SET_REG(UART_REG(uart, UxSTA), (1 << 12) | (1 << 10)); |
paul@0 | 420 | |
paul@0 | 421 | /* Start UART. */ |
paul@0 | 422 | |
paul@7 | 423 | SET_REG(UART_REG(uart, UxMODE), 1 << 15); |
paul@3 | 424 | } |
paul@3 | 425 | |
paul@3 | 426 | |
paul@3 | 427 | |
paul@3 | 428 | /* Utility functions. */ |
paul@3 | 429 | |
paul@3 | 430 | /* Return encoded interrupt priorities. */ |
paul@3 | 431 | |
paul@3 | 432 | static uint8_t PRI(uint8_t pri, uint8_t sub) |
paul@3 | 433 | { |
paul@3 | 434 | return ((pri & 0b111) << 2) | (sub & 0b11); |
paul@3 | 435 | } |
paul@3 | 436 | |
paul@10 | 437 | /* Return the DMA interrupt flags for combining with a register. */ |
paul@10 | 438 | |
paul@10 | 439 | int DMA_INT_FLAGS(int channel, uint8_t flags) |
paul@10 | 440 | { |
paul@10 | 441 | return (flags & 0b1) << (DMAINTBASE + (channel - DCHMIN)); |
paul@10 | 442 | } |
paul@10 | 443 | |
paul@3 | 444 | /* Return encoded DMA interrupt priorities for combining with a register. */ |
paul@3 | 445 | |
paul@3 | 446 | uint32_t DMA_IPC_PRI(int channel, uint8_t pri, uint8_t sub) |
paul@3 | 447 | { |
paul@3 | 448 | return PRI(pri, sub) << (DCHIPCBASE + (channel - DCHMIN) * DCHIPCSTEP); |
paul@0 | 449 | } |
paul@3 | 450 | |
paul@14 | 451 | /* Return encoded output compare interrupt priorities for combining with a register. */ |
paul@14 | 452 | |
paul@14 | 453 | uint32_t OC_IPC_PRI(int unit, uint8_t pri, uint8_t sub) |
paul@14 | 454 | { |
paul@14 | 455 | (void) unit; |
paul@14 | 456 | return PRI(pri, sub) << OCIPCBASE; |
paul@14 | 457 | } |
paul@14 | 458 | |
paul@14 | 459 | /* Return the output compare interrupt priorities register. */ |
paul@14 | 460 | |
paul@14 | 461 | uint32_t OC_IPC_REG(int unit) |
paul@14 | 462 | { |
paul@14 | 463 | switch (unit) |
paul@14 | 464 | { |
paul@14 | 465 | case 1: return OC1IPC; |
paul@14 | 466 | case 2: return OC2IPC; |
paul@14 | 467 | case 3: return OC3IPC; |
paul@14 | 468 | case 4: return OC4IPC; |
paul@14 | 469 | case 5: return OC5IPC; |
paul@14 | 470 | default: return 0; /* should not occur */ |
paul@14 | 471 | } |
paul@14 | 472 | } |
paul@14 | 473 | |
paul@14 | 474 | /* Return the output compare interrupt flags for combining with a register. */ |
paul@14 | 475 | |
paul@14 | 476 | int OC_INT_FLAGS(int unit, uint8_t flags) |
paul@14 | 477 | { |
paul@14 | 478 | return (flags & 0b1) << (OCINTBASE + (unit - OCMIN) * OCINTSTEP); |
paul@14 | 479 | } |
paul@14 | 480 | |
paul@7 | 481 | /* Return encoded timer interrupt priorities for combining with a register. */ |
paul@7 | 482 | |
paul@7 | 483 | uint32_t TIMER_IPC_PRI(int timer, uint8_t pri, uint8_t sub) |
paul@7 | 484 | { |
paul@7 | 485 | (void) timer; |
paul@7 | 486 | return PRI(pri, sub) << TIMERIPCBASE; |
paul@7 | 487 | } |
paul@7 | 488 | |
paul@7 | 489 | /* Return the timer interrupt priorities register. */ |
paul@7 | 490 | |
paul@7 | 491 | uint32_t TIMER_IPC_REG(int timer) |
paul@7 | 492 | { |
paul@7 | 493 | switch (timer) |
paul@7 | 494 | { |
paul@7 | 495 | case 1: return TIMER1IPC; |
paul@7 | 496 | case 2: return TIMER2IPC; |
paul@7 | 497 | case 3: return TIMER3IPC; |
paul@7 | 498 | case 4: return TIMER4IPC; |
paul@7 | 499 | case 5: return TIMER5IPC; |
paul@7 | 500 | default: return 0; /* should not occur */ |
paul@7 | 501 | } |
paul@7 | 502 | } |
paul@7 | 503 | |
paul@7 | 504 | /* Return the timer interrupt flags for combining with a register. */ |
paul@7 | 505 | |
paul@7 | 506 | int TIMER_INT_FLAGS(int timer, uint8_t flags) |
paul@7 | 507 | { |
paul@7 | 508 | return (flags & 0b1) << (TIMERINTBASE + (timer - TIMERMIN) * TIMERINTSTEP); |
paul@7 | 509 | } |
paul@7 | 510 | |
paul@3 | 511 | /* Return encoded UART interrupt priorities for combining with a register. */ |
paul@3 | 512 | |
paul@7 | 513 | uint32_t UART_IPC_PRI(int uart, uint8_t pri, uint8_t sub) |
paul@3 | 514 | { |
paul@7 | 515 | return PRI(pri, sub) << (uart == 1 ? UART1IPCBASE : UART2IPCBASE); |
paul@3 | 516 | } |
paul@3 | 517 | |
paul@3 | 518 | /* Return the UART interrupt priorities register. */ |
paul@3 | 519 | |
paul@7 | 520 | uint32_t UART_IPC_REG(int uart) |
paul@3 | 521 | { |
paul@7 | 522 | return uart == 1 ? UART1IPC : UART2IPC; |
paul@3 | 523 | } |
paul@3 | 524 | |
paul@7 | 525 | /* Return the UART interrupt flags for combining with a register. */ |
paul@3 | 526 | |
paul@7 | 527 | int UART_INT_FLAGS(int uart, uint8_t flags) |
paul@3 | 528 | { |
paul@7 | 529 | return (flags & 0b111) << (UARTINTBASE + (uart - UARTMIN) * UARTINTSTEP); |
paul@3 | 530 | } |