| paul@31 | 1 | Introduction
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| paul@31 | 2 | ------------
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| paul@31 | 3 |
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| paul@36 | 4 | This example demonstrates the generation of an analogue VGA signal from a
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| paul@36 | 5 | PIC32 microcontroller using general output pins. It follows on from the work
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| paul@36 | 6 | done in the VGAPIC32 project. The result is not entirely satisfactory:
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| paul@31 | 7 |
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| paul@36 | 8 | * Every fourth pixel is wider than the others, this apparently being an
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| paul@36 | 9 | artefact of the DMA transfer mechanism.
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| paul@31 | 10 |
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| paul@46 | 11 | It might be possible to introduce some kind of delay and even out the pixel
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| paul@46 | 12 | widths, but this has not been investigated with hardware. However, unlike the
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| paul@46 | 13 | vga-pmp example, there is no accompanying signal to potentially orchestrate
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| paul@46 | 14 | the staging of individual pixels at a slightly delayed rate.
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| paul@46 | 15 |
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| paul@46 | 16 | Attempts to introduce other remedies to the wide pixel problem have been made
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| paul@46 | 17 | with the vga-dual and vga-timer examples.
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| paul@31 | 18 |
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| paul@31 | 19 | Hardware Details
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| paul@31 | 20 | ================
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| paul@31 | 21 |
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| paul@31 | 22 | The pin usage of this solution is documented below.
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| paul@31 | 23 |
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| paul@31 | 24 | PIC32MX270F256B-50I/SP Pin Assignments
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| paul@31 | 25 | --------------------------------------
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| paul@31 | 26 |
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| paul@31 | 27 | MCLR# 1 \/ 28
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| paul@31 | 28 | HSYNC/OC1/RA0 2 27
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| paul@31 | 29 | VSYNC/OC2/RA1 3 26 RB15/U1TX
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| paul@31 | 30 | D0/RB0 4 25 RB14
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| paul@31 | 31 | D1/RB1 5 24 RB13/U1RX
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| paul@31 | 32 | D2/RB2 6 23
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| paul@31 | 33 | D3/RB3 7 22 RB11/PGEC2
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| paul@31 | 34 | 8 21 RB10/PGEC3
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| paul@31 | 35 | RA2 9 20
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| paul@31 | 36 | RA3 10 19
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| paul@31 | 37 | D4/RB4 11 18 RB9
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| paul@31 | 38 | 12 17 RB8
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| paul@31 | 39 | 13 16 RB7/D7
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| paul@31 | 40 | D5/RB5 14 15
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| paul@31 | 41 |
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| paul@31 | 42 | Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
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| paul@31 | 43 | unlike the MX170 variant).
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| paul@31 | 44 |
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| paul@31 | 45 | UART Connections
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| paul@31 | 46 | ----------------
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| paul@31 | 47 |
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| paul@31 | 48 | UART1 is exposed by the RB13 and RB15 pins.
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| paul@31 | 49 |
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| paul@31 | 50 | Data Signal Routing
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| paul@31 | 51 | -------------------
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| paul@31 | 52 |
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| paul@31 | 53 | For one bit of intensity, two bits per colour channel:
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| paul@31 | 54 |
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| paul@31 | 55 | D7 -> 2200R -> I
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| paul@31 | 56 |
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| paul@31 | 57 | I -> diode -> R
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| paul@31 | 58 | I -> diode -> G
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| paul@31 | 59 | I -> diode -> B
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| paul@31 | 60 |
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| paul@31 | 61 | D6 (not connected)
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| paul@31 | 62 |
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| paul@31 | 63 | D5 -> 470R -> R
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| paul@31 | 64 | D4 -> 1000R -> R
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| paul@31 | 65 | D3 -> 470R -> G
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| paul@31 | 66 | D2 -> 1000R -> G
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| paul@31 | 67 | D1 -> 470R -> B
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| paul@31 | 68 | D0 -> 1000R -> B
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| paul@31 | 69 |
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| paul@31 | 70 | HSYNC -> HS
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| paul@31 | 71 | VSYNC -> VS
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| paul@31 | 72 |
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| paul@31 | 73 | Output Socket Pinout
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| paul@31 | 74 | --------------------
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| paul@31 | 75 |
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| paul@31 | 76 | 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
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| paul@31 | 77 |
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| paul@31 | 78 | 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
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| paul@31 | 79 |
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| paul@31 | 80 | 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
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| paul@31 | 81 |
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| paul@31 | 82 | Output Cable Pinout
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| paul@31 | 83 | -------------------
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| paul@31 | 84 |
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| paul@31 | 85 | 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
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| paul@31 | 86 |
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| paul@31 | 87 | 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
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| paul@31 | 88 |
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| paul@31 | 89 | 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
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| paul@31 | 90 |
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| paul@31 | 91 | References
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| paul@31 | 92 | ----------
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| paul@31 | 93 |
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| paul@31 | 94 | https://en.wikipedia.org/wiki/VGA_connector
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| paul@31 | 95 |
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| paul@31 | 96 | http://papilio.cc/index.php?n=Papilio.VGAWing
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| paul@31 | 97 |
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| paul@31 | 98 | http://lucidscience.com/pro-vga%20video%20generator-2.aspx
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| paul@31 | 99 |
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| paul@31 | 100 | https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
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