1.1 --- a/main.c Thu Oct 18 21:05:18 2018 +0200
1.2 +++ b/main.c Thu Oct 18 22:45:55 2018 +0200
1.3 @@ -47,27 +47,40 @@
1.4 HW_PHYSICAL(UART_REG(1, UxTXREG)), 1,
1.5 1);
1.6
1.7 - /* Enable DMA on the preceding channel's completion, with Timer3 initiating
1.8 - transfers, raising a transfer completion interrupt. */
1.9 + /* Enable DMA on the preceding channel's completion, with OC1 initiating
1.10 + transfers, raising a transfer completion interrupt to be handled. */
1.11
1.12 dma_init(1, 3);
1.13 dma_set_chaining(1, dma_chain_previous);
1.14 - dma_set_interrupt(1, T3, 1);
1.15 + dma_set_interrupt(1, OC1, 1);
1.16 dma_set_transfer(1, PHYSICAL((uint32_t) message2), sizeof(message2) - 1,
1.17 HW_PHYSICAL(UART_REG(1, UxTXREG)), 1,
1.18 1);
1.19 dma_init_interrupt(1, 0b00001000, 7, 3);
1.20
1.21 - /* Configure timers. */
1.22 + /* Configure a timer for the first DMA channel whose interrupt condition
1.23 + drives the transfer but is not handled (having a lower priority than the
1.24 + CPU. */
1.25
1.26 timer_init(2, 0b111, 60000);
1.27 timer_init_interrupt(2, 1, 3);
1.28 timer_on(2);
1.29
1.30 - timer_init(3, 0b111, 40000);
1.31 - timer_init_interrupt(3, 1, 3);
1.32 + /* Configure a timer for the output compare unit below. */
1.33 +
1.34 + timer_init(3, 0b111, 20000);
1.35 timer_on(3);
1.36
1.37 + /* Configure output compare in dual compare (continuous output) mode using
1.38 + Timer3 as time base. The interrupt condition drives the second DMA
1.39 + channel but is not handled (having a lower priority than the CPU). */
1.40 +
1.41 + oc_init(1, 0b101, 3);
1.42 + oc_set_pulse(1, 10000);
1.43 + oc_set_pulse_end(1, 20000);
1.44 + oc_init_interrupt(1, 1, 3);
1.45 + oc_on(1);
1.46 +
1.47 /* Set UART interrupt priority above CPU priority to process events. */
1.48
1.49 uart_init(1, 115200);