1.1 --- a/examples/vga-timer/README.txt Tue Oct 23 19:29:55 2018 +0200
1.2 +++ b/examples/vga-timer/README.txt Tue Oct 23 21:34:54 2018 +0200
1.3 @@ -23,33 +23,43 @@
1.4 more readily delayed by other activity in the system, and with instability of
1.5 the picture being the result.
1.6
1.7 +Unlike the vga example, but in common with the vga-dual example, this example
1.8 +employs two DMA channels for pixel data which are interleaved to investigate a
1.9 +potential remedy for the wide pixel effect. This seems to preserve consistent
1.10 +pixel widths only with a transfer cell size of 1: other cell sizes suffer from
1.11 +the wide pixel problem. Despite not offering the greater throughput of larger
1.12 +cell sizes, merely employing dual channels increases throughput for a cell
1.13 +size of 1, making the technique worth using.
1.14 +
1.15 In contrast to the vga and vga-pmp examples, a special DMA channel is employed
1.16 to initiate the pixel transfer process without actually transferring any pixel
1.17 data itself. The channel arrangement is as follows:
1.18
1.19 Transfer Initiator DMA Channel Transfer Activity
1.20 ------------------ ----------- -----------------
1.21 - Timer2 DMA0 zerodata -> PORTB
1.22 - Timer3 DMA1 linedata -> PORTB
1.23 - DMA1 (completion) DMA2 zerodata -> PORTB
1.24 + Timer2 DMA1 zerodata -> PORTB
1.25 + Timer3 DMA0 linedata -> PORTB
1.26 + Timer3 DMA2 linedata -> PORTB
1.27 + Timer3 DMA3 zerodata -> PORTB
1.28
1.29 -The real purpose of this channel (DMA0) is to capture the Timer2 interrupt
1.30 -condition and to enable the following channel (DMA1) through channel chaining.
1.31 -Having been enabled, DMA1 is then able to conduct transfers at a tempo
1.32 -dictated by Timer3. Finally, DMA2 acts as the "reset" or "zero" channel to
1.33 -ensure that the pixel level is set to black at the end of each display line.
1.34 +The real purpose of this channel (DMA1) is to capture the Timer2 interrupt
1.35 +condition and to enable the following channels (DMA0, DMA2) through channel
1.36 +chaining. Having been enabled, DMA0 and DMA2 are then able to conduct
1.37 +transfers at a tempo dictated by Timer3. Finally, DMA3 acts as the "reset" or
1.38 +"zero" channel to ensure that the pixel level is set to black at the end of
1.39 +each display line.
1.40
1.41 In principle, other initiating conditions can be used instead of Timer3, which
1.42 is configured to produce such conditions as frequently as possible:
1.43
1.44 * A persistent interrupt condition can be employed instead. For example,
1.45 configuring UART2 and setting the UART2 transfer interrupt, employing this
1.46 - interrupt condition for DMA1, produces the same effect.
1.47 + interrupt condition for DMA0 and DMA2, produces the same effect.
1.48
1.49 * An external interrupt such as INT2 can be configured, and the peripheral
1.50 clock can be routed through the CLKO pin and back into the microcontroller
1.51 via an appropriate pin. With INT2 being employed as the interrupt
1.52 - condition for DMA1, the same effect is produced.
1.53 + condition for DMA0 and DMA2, the same effect is produced.
1.54
1.55 Hardware Details
1.56 ================