1.1 --- a/examples/vga-timer/main.c Tue Oct 23 19:29:55 2018 +0200
1.2 +++ b/examples/vga-timer/main.c Tue Oct 23 21:34:54 2018 +0200
1.3 @@ -98,44 +98,55 @@
1.4
1.5 Timer2 -> OC1
1.6 -> OC2 (vertical sync region)
1.7 - -> DMA0: zerodata -> PORTB (visible region)
1.8 + -> DMA1: zerodata -> PORTB (visible region)
1.9 |
1.10 - Timer3 -> DMA1: linedata -> PORTB
1.11 + Timer3 -> DMA0: linedata -> PORTB
1.12 + Timer3 -> DMA2: linedata -> PORTB
1.13 |
1.14 - Timer3 -> DMA2: zerodata -> PORTB
1.15 + Timer3 -> DMA3: zerodata -> PORTB
1.16 */
1.17
1.18 /* Initiate DMA on the Timer2 interrupt condition, transferring line data to
1.19 the first byte of PORTB. Do not enable the channel for initiation until
1.20 the visible region is about to start. */
1.21
1.22 - dma_init(0, 3);
1.23 - dma_set_auto_enable(0, 1);
1.24 - dma_set_interrupt(0, T2, 1);
1.25 - dma_set_transfer(0, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH,
1.26 + dma_init(1, 3);
1.27 + dma_set_auto_enable(1, 1);
1.28 + dma_set_interrupt(1, T2, 1);
1.29 + dma_set_transfer(1, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH,
1.30 HW_PHYSICAL(PORTB), 1,
1.31 ZERO_LENGTH);
1.32
1.33 - /* Enable DMA on the preceding channel's completion, with the Timer3
1.34 + /* Enable DMA on the zero channel's completion, with the Timer3
1.35 interrupt condition initiating transfers. */
1.36
1.37 - dma_init(1, 3);
1.38 - dma_set_chaining(1, dma_chain_previous);
1.39 - dma_set_interrupt(1, T3, 1);
1.40 - dma_set_transfer(1, PHYSICAL((uint32_t) screenstart), LINE_LENGTH,
1.41 + dma_init(0, 3);
1.42 + dma_set_chaining(0, dma_chain_next);
1.43 + dma_set_interrupt(0, T3, 1);
1.44 + dma_set_transfer(0, PHYSICAL((uint32_t) screenstart), LINE_LENGTH / 2,
1.45 HW_PHYSICAL(PORTB), 1,
1.46 - 1);
1.47 + TRANSFER_CELL_SIZE);
1.48 +
1.49 + /* Enable DMA on the zero channel's completion, with the Timer3
1.50 + interrupt condition initiating transfers. */
1.51 +
1.52 + dma_init(2, 3);
1.53 + dma_set_chaining(2, dma_chain_previous);
1.54 + dma_set_interrupt(2, T3, 1);
1.55 + dma_set_transfer(2, PHYSICAL((uint32_t) screenstart + LINE_LENGTH / 2), LINE_LENGTH / 2,
1.56 + HW_PHYSICAL(PORTB), 1,
1.57 + TRANSFER_CELL_SIZE);
1.58
1.59 /* Enable DMA on the preceding channel's completion, with this also
1.60 initiating transfers. */
1.61
1.62 - dma_init(2, 3);
1.63 - dma_set_chaining(2, dma_chain_previous);
1.64 - dma_set_interrupt(2, T3, 1);
1.65 - dma_set_transfer(2, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH,
1.66 + dma_init(3, 3);
1.67 + dma_set_chaining(3, dma_chain_previous);
1.68 + dma_set_interrupt(3, T3, 1);
1.69 + dma_set_transfer(3, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH,
1.70 HW_PHYSICAL(PORTB), 1,
1.71 ZERO_LENGTH);
1.72 - dma_set_receive_events(2, 1);
1.73 + dma_set_receive_events(3, 1);
1.74
1.75 /* Configure a timer for the horizontal sync. The timer has no prescaling
1.76 (0). */
1.77 @@ -218,11 +229,12 @@
1.78 /* Set the line address. */
1.79
1.80 linedata = screenstart;
1.81 - dma_set_source(1, PHYSICAL((uint32_t) linedata), LINE_LENGTH);
1.82 + dma_set_source(0, PHYSICAL((uint32_t) linedata), LINE_LENGTH / 2);
1.83 + dma_set_source(2, PHYSICAL((uint32_t) linedata + LINE_LENGTH / 2), LINE_LENGTH / 2);
1.84
1.85 - /* Enable the channel for the next line. */
1.86 + /* Enable the channels for the next line. */
1.87
1.88 - dma_on(0);
1.89 + dma_on(1);
1.90 }
1.91
1.92 /* Visible region. */
1.93 @@ -242,7 +254,8 @@
1.94 linedata -= SCREEN_SIZE;
1.95 }
1.96
1.97 - dma_set_source(1, PHYSICAL((uint32_t) linedata), LINE_LENGTH);
1.98 + dma_set_source(0, PHYSICAL((uint32_t) linedata), LINE_LENGTH / 2);
1.99 + dma_set_source(2, PHYSICAL((uint32_t) linedata + LINE_LENGTH / 2), LINE_LENGTH / 2);
1.100 return;
1.101 }
1.102
1.103 @@ -250,9 +263,9 @@
1.104
1.105 state_handler = vfp_active;
1.106
1.107 - /* Disable the channel for the next line. */
1.108 + /* Disable the channels for the next line. */
1.109
1.110 - dma_off(0);
1.111 + dma_off(1);
1.112 }
1.113
1.114 /* Vertical front porch region. */