1.1 --- a/examples/vga/main.c Wed Oct 24 13:21:21 2018 +0200
1.2 +++ b/examples/vga/main.c Wed Oct 24 15:31:56 2018 +0200
1.3 @@ -106,32 +106,10 @@
1.4 ZERO_LENGTH);
1.5 dma_set_receive_events(1, 1);
1.6
1.7 - /* Configure a timer for the horizontal sync. The timer has no prescaling
1.8 - (0). */
1.9 -
1.10 - timer_init(2, 0, HFREQ_LIMIT);
1.11 - timer_on(2);
1.12 -
1.13 - /* Horizontal sync. */
1.14 -
1.15 - /* Configure output compare in dual compare (continuous output) mode using
1.16 - Timer2 as time base. The interrupt condition drives the first DMA channel
1.17 - and is handled to drive the display state machine. */
1.18 + /* Configure a timer and output compare units for horizontal and vertical
1.19 + sync. */
1.20
1.21 - oc_init(1, 0b101, 2);
1.22 - oc_set_pulse(1, HSYNC_END);
1.23 - oc_set_pulse_end(1, HSYNC_START);
1.24 - oc_init_interrupt(1, 7, 3);
1.25 - oc_on(1);
1.26 -
1.27 - /* Vertical sync. */
1.28 -
1.29 - /* Configure output compare in single compare (output driven low) mode using
1.30 - Timer2 as time base. The unit is enabled later. It is only really used to
1.31 - achieve precisely-timed level transitions in hardware. */
1.32 -
1.33 - oc_init(2, 0b010, 2);
1.34 - oc_set_pulse(2, 0);
1.35 + vga_configure_sync(1, 2, 2);
1.36
1.37 uart_init(1, FPB, 115200);
1.38 uart_on(1);