1.1 --- a/examples/vga-timer/devconfig.h Thu Oct 25 21:11:22 2018 +0200
1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
1.3 @@ -1,63 +0,0 @@
1.4 -/*
1.5 - * Device configuration.
1.6 - *
1.7 - * Copyright (C) 2018 Paul Boddie <paul@boddie.org.uk>
1.8 - *
1.9 - * This program is free software: you can redistribute it and/or modify
1.10 - * it under the terms of the GNU General Public License as published by
1.11 - * the Free Software Foundation, either version 3 of the License, or
1.12 - * (at your option) any later version.
1.13 - *
1.14 - * This program is distributed in the hope that it will be useful,
1.15 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 - * GNU General Public License for more details.
1.18 - *
1.19 - * You should have received a copy of the GNU General Public License
1.20 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
1.21 - */
1.22 -
1.23 -#ifndef __CONFIG_H__
1.24 -#define __CONFIG_H__
1.25 -
1.26 -#include "pic32.h"
1.27 -
1.28 -/*
1.29 -Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
1.30 -divided by 2 (FPBDIV), and FRCDIV+PLL selected (FNOSC).
1.31 -
1.32 -The watchdog timer (FWDTEN) is also disabled.
1.33 -
1.34 -The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
1.35 -RPB4.
1.36 -*/
1.37 -
1.38 -#define DEVCFG1_CONFIG (DEVCFG1_FWDTEN_OFF | DEVCFG1_FPBDIV_2 | \
1.39 - DEVCFG1_OSCIOFNC_OFF | DEVCFG1_FSOSCEN_OFF | \
1.40 - DEVCFG1_FNOSC_FRCDIV_PLL)
1.41 -
1.42 -/*
1.43 -Set the FRC oscillator PLL function with an input division of 2, an output
1.44 -division of 2, a multiplication of 24, yielding a multiplication of 6.
1.45 -
1.46 -The FRC is apparently at 8MHz but enforces input division of 2 to produce a
1.47 -frequency in the acceptable range from 4MHz to 5MHz for the PLL:
1.48 -
1.49 -8MHz / 2 = 4MHz
1.50 -
1.51 -Multiplication and output division should produce a system clock of 48MHz:
1.52 -
1.53 -4MHz * 24 / 2 = 48MHz
1.54 -*/
1.55 -
1.56 -#define DEVCFG2_CONFIG (DEVCFG2_FPLLODIV_2 | DEVCFG2_FPLLMUL_24 | \
1.57 - DEVCFG2_FPLLIDIV_2)
1.58 -
1.59 -/*
1.60 -The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1 and
1.61 -DEVCFG2 settings.
1.62 -*/
1.63 -
1.64 -#define FPB 24000000
1.65 -
1.66 -#endif /* __CONFIG_H__ */