1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/lib/cpu.S Mon Oct 22 21:44:02 2018 +0200
1.3 @@ -0,0 +1,174 @@
1.4 +/*
1.5 + * PIC32 microcontroller interrupt handling code.
1.6 + *
1.7 + * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>
1.8 + *
1.9 + * This program is free software: you can redistribute it and/or modify
1.10 + * it under the terms of the GNU General Public License as published by
1.11 + * the Free Software Foundation, either version 3 of the License, or
1.12 + * (at your option) any later version.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1.21 + */
1.22 +
1.23 +#include "mips.h"
1.24 +#include "pic32.h"
1.25 +#include "cpu.h"
1.26 +
1.27 +.globl enable_interrupts
1.28 +.globl handle_error_level
1.29 +.globl init_interrupts
1.30 +.extern exception_handler
1.31 +.extern interrupt_handler
1.32 +
1.33 +/* Put general routines in the text section. */
1.34 +
1.35 +.text
1.36 +
1.37 +/*
1.38 +Clear the error and exception status flags, making interrupts and exceptions
1.39 +possible.
1.40 +*/
1.41 +
1.42 +handle_error_level:
1.43 + mfc0 $t3, CP0_STATUS
1.44 +
1.45 + /* Clear error level and exception level. */
1.46 +
1.47 + li $t4, ~(STATUS_ERL | STATUS_EXL)
1.48 + and $t3, $t3, $t4
1.49 + mtc0 $t3, CP0_STATUS
1.50 +
1.51 + jr $ra
1.52 + nop
1.53 +
1.54 +/* Enable interrupts and direct interrupt requests to non-bootloader vectors. */
1.55 +
1.56 +enable_interrupts:
1.57 + mfc0 $t3, CP0_STATUS
1.58 +
1.59 + /* Clear interrupt priority bits. */
1.60 +
1.61 + li $t4, ~STATUS_IRQ
1.62 + and $t3, $t3, $t4
1.63 +
1.64 + /* Set interrupt priority. */
1.65 +
1.66 + ori $t3, $t3, (CPU_INT_PRIORITY << STATUS_IRQ_SHIFT)
1.67 +
1.68 + /* CP0_STATUS &= ~STATUS_BEV (use non-bootloader vectors) */
1.69 +
1.70 + li $t4, ~STATUS_BEV
1.71 + and $t3, $t3, $t4
1.72 +
1.73 + /* Enable interrupts. */
1.74 +
1.75 + ori $t3, $t3, STATUS_IE
1.76 + mtc0 $t3, CP0_STATUS
1.77 +
1.78 + jr $ra
1.79 + nop
1.80 +
1.81 +/* Initialise the interrupt system parameters. */
1.82 +
1.83 +init_interrupts:
1.84 + /* Clear debug mode. */
1.85 +
1.86 + mfc0 $t3, CP0_DEBUG
1.87 + li $t4, ~DEBUG_DM
1.88 + and $t3, $t3, $t4
1.89 + mtc0 $t3, CP0_DEBUG
1.90 +
1.91 + /* Update the exception base. */
1.92 +
1.93 + mfc0 $t3, CP0_STATUS
1.94 + li $t4, STATUS_BEV /* BEV = 1 or EBASE cannot be set */
1.95 + or $t3, $t3, $t4
1.96 + mtc0 $t3, CP0_STATUS
1.97 +
1.98 + la $t3, ebase
1.99 + mtc0 $t3, CP0_EBASE
1.100 +
1.101 + /* Set vector spacing. */
1.102 +
1.103 + li $t3, 0x20 /* Must be non-zero or the CPU gets upset */
1.104 + mtc0 $t3, CP0_INTCTL
1.105 +
1.106 + li $t3, CAUSE_IV /* IV = 1 (use EBASE+0x200 for interrupts) */
1.107 + mtc0 $t3, CP0_CAUSE
1.108 +
1.109 + jr $ra
1.110 + nop
1.111 +
1.112 +
1.113 +
1.114 +/* Exception servicing, positioned at EBASE at the start of program memory. */
1.115 +
1.116 +.section .vectors, "a"
1.117 +
1.118 +/* TLB error servicing. */
1.119 +
1.120 +ebase:
1.121 +tlb_handler:
1.122 + j exception_handler
1.123 + nop
1.124 +
1.125 +
1.126 +
1.127 +/* General exception servicing. */
1.128 +
1.129 +.org 0x180
1.130 +
1.131 +exc_handler:
1.132 + j exception_handler
1.133 + nop
1.134 +
1.135 +
1.136 +
1.137 +/* Interrupt servicing. */
1.138 +
1.139 +.org 0x200
1.140 +.set noat
1.141 +
1.142 +#define IRQ_STACK_LIMIT (KSEG0_BASE + IRQ_STACK_SIZE)
1.143 +#define IRQ_STACK_TOP (IRQ_STACK_LIMIT - 32 * 4)
1.144 +
1.145 +int_handler:
1.146 +
1.147 + /* Store affected registers from IRQ_STACK_LIMIT - 4 downwards. */
1.148 +
1.149 + lui $k0, %hi(IRQ_STACK_LIMIT)
1.150 + ori $k0, $k0, %lo(IRQ_STACK_LIMIT)
1.151 +
1.152 + .irp reg, \
1.153 + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 \
1.154 + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
1.155 + 28, 29, 30, 31
1.156 + sw $\reg, -(\reg * 4)($k0)
1.157 + .endr
1.158 +
1.159 + /* Switch to the IRQ stack. */
1.160 +
1.161 + lui $sp, %hi(IRQ_STACK_TOP)
1.162 + ori $sp, $sp, %lo(IRQ_STACK_TOP)
1.163 +
1.164 + jal interrupt_handler
1.165 + nop
1.166 +
1.167 + /* Restore affected registers. */
1.168 +
1.169 + .irp reg, \
1.170 + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 \
1.171 + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
1.172 + 28, 29, 30, 31
1.173 + lw $\reg, -(\reg * 4)($k0)
1.174 + .endr
1.175 +
1.176 + eret
1.177 + nop