1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/docs/wiki/Examples--vga-pmp Sat May 04 22:54:18 2019 +0200
1.3 @@ -0,0 +1,113 @@
1.4 += VGA Output Example (Parallel Mode Transfers) =
1.5 +
1.6 +This example demonstrates the generation of an analogue VGA signal from a
1.7 +PIC32 microcontroller using the parallel mode (parallel master port, PMP)
1.8 +peripheral. The result is not entirely satisfactory:
1.9 +
1.10 + * Pixels are very narrow unless buffered using a flip-flop driven by the
1.11 + peripheral, this being a characteristic of the way the peripheral works, it
1.12 + normally being used to drive memory and display controllers.
1.13 +
1.14 + * Introducing a flip-flop means that the final pixel from the pixel data
1.15 + remains asserted and must be reset using a second DMA channel.
1.16 +
1.17 + * Every fourth pixel is wider than the others, this apparently being an
1.18 + artefact of the DMA transfer mechanism.
1.19 +
1.20 +It might be possible introduce some kind of delay to the write strobe (PMWR)
1.21 +and even out the pixel widths, but this has not been investigated.
1.22 +
1.23 +It appears to be the case that the system and peripheral clock frequencies
1.24 +need to be matched. In this example, a frequency of 48MHz has been chosen.
1.25 +
1.26 +== Hardware Details ==
1.27 +
1.28 +The pin usage of this solution is documented below.
1.29 +
1.30 +=== PIC32MX270F256B-50I/SP Pin Assignments ===
1.31 +
1.32 +{{{
1.33 +MCLR# 1 \/ 28
1.34 + D7/PMD7/RA0 2 27
1.35 + D6/PMD6/RA1 3 26 RB15/U1TX
1.36 + D0/PMD0/RB0 4 25 RB14
1.37 + D1/PMD1/RB1 5 24 RB13/(PMRD)/U1RX
1.38 + D2/PMD2/RB2 6 23
1.39 + PMWR/RB3 7 22 RB11/PGEC2
1.40 + 8 21 RB10/PGEC3
1.41 + RA2 9 20
1.42 + (PMA0)/RA3 10 19
1.43 +HSYNC/OC1/RB4 11 18 RB9/PMD3/D3
1.44 + 12 17 RB8/PMD4/D4
1.45 + 13 16 RB7/PMD5/D5
1.46 +VSYNC/OC2/RB5 14 15
1.47 +}}}
1.48 +
1.49 +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
1.50 +unlike the MX170 variant).
1.51 +
1.52 +=== UART Connections ===
1.53 +
1.54 +UART1 is exposed by the RB13 and RB15 pins.
1.55 +
1.56 +=== Data Signal Routing ===
1.57 +
1.58 +A flip-flop is used to buffer the outputs:
1.59 +
1.60 +{{{
1.61 +Dn -> 74HC273:Dn
1.62 + 74HC273:Qn -> Qn
1.63 +VCC -> 74HC273:MR#
1.64 +PMWR -> 74HC273:CP
1.65 +}}}
1.66 +
1.67 +For two bits of intensity, two bits per colour channel:
1.68 +
1.69 +{{{
1.70 +Q7 -> 2200R -> I
1.71 +Q6 -> 4700R -> I
1.72 +
1.73 +I -> diode -> R
1.74 +I -> diode -> G
1.75 +I -> diode -> B
1.76 +
1.77 +Q5 -> 470R -> R
1.78 +Q4 -> 1000R -> R
1.79 +Q3 -> 470R -> G
1.80 +Q2 -> 1000R -> G
1.81 +Q1 -> 470R -> B
1.82 +Q0 -> 1000R -> B
1.83 +
1.84 +HSYNC -> HS
1.85 +VSYNC -> VS
1.86 +}}}
1.87 +
1.88 +=== Output Socket Pinout ===
1.89 +
1.90 +{{{
1.91 +5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
1.92 +
1.93 + 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
1.94 +
1.95 +15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
1.96 +}}}
1.97 +
1.98 +=== Output Cable Pinout ===
1.99 +
1.100 +{{{
1.101 + 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
1.102 +
1.103 +6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
1.104 +
1.105 + 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
1.106 +}}}
1.107 +
1.108 +== References ==
1.109 +
1.110 +https://en.wikipedia.org/wiki/VGA_connector
1.111 +
1.112 +http://papilio.cc/index.php?n=Papilio.VGAWing
1.113 +
1.114 +http://lucidscience.com/pro-vga%20video%20generator-2.aspx
1.115 +
1.116 +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga