1.1 --- a/examples/vga-timer/README.txt Thu May 02 23:21:32 2019 +0200
1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
1.3 @@ -1,145 +0,0 @@
1.4 -Introduction
1.5 -------------
1.6 -
1.7 -This example demonstrates the generation of an analogue VGA signal from a
1.8 -PIC32 microcontroller using general output pins. Unlike the vga and vga-pmp
1.9 -examples, it employs a regular interrupt condition to schedule single-byte
1.10 -(single-pixel) DMA transfers instead of a single whole-line transfer.
1.11 -
1.12 -The principal advantage of this method over the whole-line transfer method is
1.13 -its production of pixels with consistent widths. The principal disadvantage is
1.14 -the significant loss of horizontal resolution due to the latencies involved in
1.15 -propagating interrupt conditions to the DMA controller and thereby initiating
1.16 -each transfer.
1.17 -
1.18 -Employing a peripheral clock that has half the frequency of the system clock
1.19 -should ensure the stability of the picture, since the lower frequency may make
1.20 -transfers easier to schedule. The peripheral clock should provide a more
1.21 -forgiving deadline for each transfer, permitting late transfers to complete on
1.22 -time.
1.23 -
1.24 -Meanwhile, matching the system and peripheral clock frequencies appears to
1.25 -leave the scheduling of transfers open to uncertainty, with transfers being
1.26 -more readily delayed by other activity in the system, and with instability of
1.27 -the picture being the result.
1.28 -
1.29 -Unlike the vga example, but in common with the vga-dual example, this example
1.30 -employs two DMA channels for pixel data which are interleaved to investigate a
1.31 -potential remedy for the wide pixel effect. This seems to preserve consistent
1.32 -pixel widths only with a transfer cell size of 1: other cell sizes suffer from
1.33 -the wide pixel problem. Despite not offering the greater throughput of larger
1.34 -cell sizes, merely employing dual channels increases throughput for a cell
1.35 -size of 1, making the technique worth using.
1.36 -
1.37 -In contrast to the vga and vga-pmp examples, a special DMA channel is employed
1.38 -to initiate the pixel transfer process without actually transferring any pixel
1.39 -data itself. The channel arrangement is as follows:
1.40 -
1.41 - Transfer Initiator DMA Channel Transfer Activity
1.42 - ------------------ ----------- -----------------
1.43 - Timer2 DMA1 zerodata -> PORTB
1.44 - Timer3 DMA0 linedata -> PORTB
1.45 - Timer3 DMA2 linedata -> PORTB
1.46 - Timer3 DMA3 zerodata -> PORTB
1.47 -
1.48 -The real purpose of this channel (DMA1) is to capture the Timer2 interrupt
1.49 -condition and to enable the following channels (DMA0, DMA2) through channel
1.50 -chaining. Having been enabled, DMA0 and DMA2 are then able to conduct
1.51 -transfers at a tempo dictated by Timer3. Finally, DMA3 acts as the "reset" or
1.52 -"zero" channel to ensure that the pixel level is set to black at the end of
1.53 -each display line.
1.54 -
1.55 -In principle, other initiating conditions can be used instead of Timer3, which
1.56 -is configured to produce such conditions as frequently as possible:
1.57 -
1.58 - * A persistent interrupt condition can be employed instead. For example,
1.59 - configuring UART2 and setting the UART2 transfer interrupt, employing this
1.60 - interrupt condition for DMA0 and DMA2, produces the same effect.
1.61 -
1.62 - * An external interrupt such as INT2 can be configured, and the peripheral
1.63 - clock can be routed through the CLKO pin and back into the microcontroller
1.64 - via an appropriate pin. With INT2 being employed as the interrupt
1.65 - condition for DMA0 and DMA2, the same effect is produced.
1.66 -
1.67 -Hardware Details
1.68 -================
1.69 -
1.70 -The pin usage of this solution is documented below.
1.71 -
1.72 -PIC32MX270F256B-50I/SP Pin Assignments
1.73 ---------------------------------------
1.74 -
1.75 -MCLR# 1 \/ 28
1.76 -HSYNC/OC1/RA0 2 27
1.77 -VSYNC/OC2/RA1 3 26 RB15/U1TX
1.78 - D0/RB0 4 25 RB14
1.79 - D1/RB1 5 24 RB13/U1RX
1.80 - D2/RB2 6 23
1.81 - D3/RB3 7 22 RB11/PGEC2
1.82 - 8 21 RB10/PGEC3
1.83 - RA2 9 20
1.84 - RA3 10 19
1.85 - D4/RB4 11 18 RB9
1.86 - 12 17 RB8
1.87 - 13 16 RB7/D7
1.88 - D5/RB5 14 15
1.89 -
1.90 -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
1.91 -unlike the MX170 variant).
1.92 -
1.93 -UART Connections
1.94 -----------------
1.95 -
1.96 -UART1 is exposed by the RB13 and RB15 pins.
1.97 -
1.98 -Data Signal Routing
1.99 --------------------
1.100 -
1.101 -For one bit of intensity, two bits per colour channel:
1.102 -
1.103 -D7 -> 2200R -> I
1.104 -
1.105 -I -> diode -> R
1.106 -I -> diode -> G
1.107 -I -> diode -> B
1.108 -
1.109 -D6 (not connected)
1.110 -
1.111 -D5 -> 470R -> R
1.112 -D4 -> 1000R -> R
1.113 -D3 -> 470R -> G
1.114 -D2 -> 1000R -> G
1.115 -D1 -> 470R -> B
1.116 -D0 -> 1000R -> B
1.117 -
1.118 -HSYNC -> HS
1.119 -VSYNC -> VS
1.120 -
1.121 -Output Socket Pinout
1.122 ---------------------
1.123 -
1.124 - 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
1.125 -
1.126 - 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
1.127 -
1.128 - 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
1.129 -
1.130 -Output Cable Pinout
1.131 --------------------
1.132 -
1.133 - 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
1.134 -
1.135 - 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
1.136 -
1.137 - 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
1.138 -
1.139 -References
1.140 -----------
1.141 -
1.142 -https://en.wikipedia.org/wiki/VGA_connector
1.143 -
1.144 -http://papilio.cc/index.php?n=Papilio.VGAWing
1.145 -
1.146 -http://lucidscience.com/pro-vga%20video%20generator-2.aspx
1.147 -
1.148 -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga