1.1 --- a/init.c Thu Oct 18 17:58:45 2018 +0200
1.2 +++ b/init.c Thu Oct 18 18:24:48 2018 +0200
1.3 @@ -125,18 +125,36 @@
1.4
1.5 /* Initialise the given channel. */
1.6
1.7 -void dma_init(int channel, int auto_enable, uint8_t pri)
1.8 +void dma_init(int channel, uint8_t pri)
1.9 {
1.10 if ((channel < DCHMIN) || (channel > DCHMAX))
1.11 return;
1.12
1.13 /* Initialise a channel. */
1.14
1.15 - REG(DMA_REG(channel, DCHxCON)) = (auto_enable ? (1 << 4) : 0) | (pri & 0b11);
1.16 + REG(DMA_REG(channel, DCHxCON)) = pri & 0b11;
1.17 REG(DMA_REG(channel, DCHxECON)) = 0;
1.18 REG(DMA_REG(channel, DCHxINT)) = 0;
1.19 }
1.20
1.21 +/* Set the channel auto-enable mode. */
1.22 +
1.23 +void dma_set_auto_enable(int channel, int auto_enable)
1.24 +{
1.25 + (auto_enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 4);
1.26 +}
1.27 +
1.28 +/* Set the channel chaining mode. */
1.29 +
1.30 +void dma_set_chaining(int channel, enum dma_chain chain)
1.31 +{
1.32 + (chain != dma_chain_none ?
1.33 + SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 5);
1.34 +
1.35 + (chain == dma_chain_next ?
1.36 + SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 8);
1.37 +}
1.38 +
1.39 /* Configure a channel's initiation interrupt. */
1.40
1.41 void dma_set_interrupt(int channel, uint8_t int_num, int enable)
1.42 @@ -175,6 +193,11 @@
1.43 if ((channel < DCHMIN) || (channel > DCHMAX))
1.44 return;
1.45
1.46 + /* Disable channel interrupt and clear interrupt flag. */
1.47 +
1.48 + CLR_REG(DMAIEC, DMA_INT_FLAGS(channel, 1));
1.49 + CLR_REG(DMAIFS, DMA_INT_FLAGS(channel, 1));
1.50 +
1.51 /* Produce an interrupt for the provided conditions. */
1.52
1.53 REG(DMA_REG(channel, DCHxINT)) = conditions << 16;
1.54 @@ -186,7 +209,7 @@
1.55
1.56 /* Enable interrupt. */
1.57
1.58 - SET_REG(DMAIEC, 1 << (channel + DMAINTBASE));
1.59 + SET_REG(DMAIEC, DMA_INT_FLAGS(channel, 1));
1.60 }
1.61
1.62 /* Enable a DMA channel. */
1.63 @@ -320,6 +343,13 @@
1.64 return ((pri & 0b111) << 2) | (sub & 0b11);
1.65 }
1.66
1.67 +/* Return the DMA interrupt flags for combining with a register. */
1.68 +
1.69 +int DMA_INT_FLAGS(int channel, uint8_t flags)
1.70 +{
1.71 + return (flags & 0b1) << (DMAINTBASE + (channel - DCHMIN));
1.72 +}
1.73 +
1.74 /* Return encoded DMA interrupt priorities for combining with a register. */
1.75
1.76 uint32_t DMA_IPC_PRI(int channel, uint8_t pri, uint8_t sub)