1.1 --- a/start.S Mon Oct 22 13:24:20 2018 +0200
1.2 +++ b/start.S Mon Oct 22 18:25:21 2018 +0200
1.3 @@ -20,46 +20,24 @@
1.4 #include "mips.h"
1.5 #include "pic32.h"
1.6
1.7 +/* Application-specific configuration. */
1.8 +
1.9 +#include "devconfig.h"
1.10 +
1.11 /* Disable JTAG functionality on pins. */
1.12
1.13 .section .devcfg0, "a"
1.14 .word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */
1.15
1.16 -/*
1.17 -Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
1.18 -divided by 2 (FPBDIV), and FRCDIV+PLL selected (FNOSC).
1.19 -
1.20 -The watchdog timer (FWDTEN) is also disabled.
1.21 -
1.22 -The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
1.23 -RPB4.
1.24 -*/
1.25 +/* Select oscillator, pin usage, watchdog timer and peripheral clock divider. */
1.26
1.27 .section .devcfg1, "a"
1.28 -.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 01;
1.29 - DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
1.30 -
1.31 -/*
1.32 -Set the FRC oscillator PLL function with an input division of 2, an output
1.33 -division of 2, a multiplication of 24, yielding a multiplication of 6.
1.34 -
1.35 -The FRC is apparently at 8MHz but enforces input division of 2 to produce a
1.36 -frequency in the acceptable range from 4MHz to 5MHz for the PLL:
1.37 +.word (DEVCFG1_UNUSED | DEVCFG1_CONFIG)
1.38
1.39 -8MHz / 2 = 4MHz
1.40 -
1.41 -Multiplication and output division should produce a system clock of 48MHz:
1.42 -
1.43 -4MHz * 24 / 2 = 48MHz
1.44 -
1.45 -The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1
1.46 -settings.
1.47 -*/
1.48 +/* Set clock dividers and multiplier. */
1.49
1.50 .section .devcfg2, "a"
1.51 -.word 0xfff9fff9 /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
1.52 - DEVCFG2<6:4> = FPLLMUL<2:0> = 111;
1.53 - DEVCFG2<2:0> = FPLLIDIV<2:0> = 001 */
1.54 +.word (DEVCFG2_UNUSED | DEVCFG2_CONFIG)
1.55
1.56 /* The start routine is placed at the boot location. */
1.57