1 #ifndef __PIC32_H__ 2 #define __PIC32_H__ 3 4 /* Peripheral addresses. 5 * See... 6 * TABLE 4-1: SFR MEMORYMAP 7 * TABLE 11-3: PORTA REGISTER MAP 8 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 9 */ 10 11 #define PMCON 0xBF807000 12 #define PMMODE 0xBF807010 13 #define PMADDR 0xBF807020 14 #define PMDOUT 0xBF807030 15 #define PMDIN 0xBF807040 16 #define PMAEN 0xBF807050 17 #define PMSTAT 0xBF807060 18 19 #define OSCCON 0xBF80F000 20 #define REFOCON 0xBF80F020 21 #define REFOTRIM 0xBF80F030 22 #define CFGCON 0xBF80F200 23 #define SYSKEY 0xBF80F230 24 25 #define U1RXR 0xBF80FA50 26 27 #define RPA0R 0xBF80FB00 28 #define RPA1R 0xBF80FB04 29 #define RPA2R 0xBF80FB08 30 #define RPA3R 0xBF80FB0C 31 #define RPA4R 0xBF80FB10 32 #define RPB0R 0xBF80FB2C 33 #define RPB1R 0xBF80FB30 34 #define RPB2R 0xBF80FB34 35 #define RPB3R 0xBF80FB38 36 #define RPB4R 0xBF80FB3C 37 #define RPB5R 0xBF80FB40 38 #define RPB10R 0xBF80FB54 39 #define RPB15R 0xBF80FB68 40 41 #define INTCON 0xBF881000 42 #define IFS0 0xBF881030 43 #define IFS1 0xBF881040 44 #define IEC0 0xBF881060 45 #define IEC1 0xBF881070 46 #define IPC1 0xBF8810A0 47 #define IPC2 0xBF8810B0 48 #define IPC3 0xBF8810C0 49 #define IPC4 0xBF8810D0 50 #define IPC5 0xBF8810E0 51 #define IPC6 0xBF8810F0 52 #define IPC7 0xBF881100 53 #define IPC8 0xBF881110 54 #define IPC9 0xBF881120 55 #define IPC10 0xBF881130 56 57 #define BMXCON 0xBF882000 58 #define BMXDKPBA 0xBF882010 59 #define BMXDUDBA 0xBF882020 60 #define BMXDUPBA 0xBF882030 61 #define BMXDRMSZ 0xBF882040 62 63 #define ANSELA 0xBF886000 64 #define TRISA 0xBF886010 65 #define PORTA 0xBF886020 66 #define LATA 0xBF886030 67 #define ODCA 0xBF886040 68 #define ANSELB 0xBF886100 69 #define TRISB 0xBF886110 70 #define PORTB 0xBF886120 71 #define LATB 0xBF886130 72 #define ODCB 0xBF886140 73 74 /* DMA conveniences. */ 75 76 #define DMACON 0xBF883000 77 #define DCH0CON 0xBF883060 78 #define DCH1CON 0xBF883120 79 #define DCH2CON 0xBF8831E0 80 #define DCH3CON 0xBF8832A0 81 82 #define DCHMIN 0 83 #define DCHMAX 3 84 #define DCHBASE DCH0CON 85 #define DCHSTEP (DCH1CON - DCH0CON) 86 87 #define DCHxCON 0x00 88 #define DCHxECON 0x10 89 #define DCHxINT 0x20 90 #define DCHxSSA 0x30 91 #define DCHxDSA 0x40 92 #define DCHxSSIZ 0x50 93 #define DCHxDSIZ 0x60 94 #define DCHxSPTR 0x70 95 #define DCHxDPTR 0x80 96 #define DCHxCSIZ 0x90 97 #define DCHxCPTR 0xA0 98 #define DCHxDAT 0xB0 99 100 #define DMAIEC IEC1 101 #define DMAIFS IFS1 102 #define DMAINTBASE 28 103 104 #define DMAIPC IPC10 105 #define DCHIPCBASE 0 106 #define DCHIPCSTEP 8 107 108 /* Output compare conveniences. */ 109 110 #define OC1CON 0xBF803000 111 #define OC2CON 0xBF803200 112 #define OC3CON 0xBF803400 113 #define OC4CON 0xBF803600 114 #define OC5CON 0xBF803800 115 116 #define OCMIN 1 117 #define OCMAX 5 118 #define OCBASE OC1CON 119 #define OCSTEP (OC2CON - OC1CON) 120 121 #define OCxCON 0x00 122 #define OCxR 0x10 123 #define OCxRS 0x20 124 125 #define OCIEC IEC0 126 127 #define OCxIE 1 128 129 #define OCIFS IFS0 130 131 #define OCxIF 1 132 133 #define OCINTBASE 7 134 #define OCINTSTEP 5 135 136 #define OC1IPC IPC1 137 #define OC2IPC IPC2 138 #define OC3IPC IPC3 139 #define OC4IPC IPC4 140 #define OC5IPC IPC5 141 #define OCIPCBASE 16 142 143 /* Timer conveniences. */ 144 145 #define T1CON 0xBF800600 146 #define T2CON 0xBF800800 147 #define T3CON 0xBF800A00 148 #define T4CON 0xBF800C00 149 #define T5CON 0xBF800E00 150 151 #define TIMERMIN 1 152 #define TIMERMAX 5 153 #define TIMERBASE T1CON 154 #define TIMERSTEP (T2CON - T1CON) 155 156 #define TxCON 0x00 157 #define TMRx 0x10 158 #define PRx 0x20 159 160 #define TIMERIEC IEC0 161 162 #define TxIE 1 163 164 #define TIMERIFS IEC0 165 166 #define TxIF 1 167 168 #define TIMERINTBASE 4 169 #define TIMERINTSTEP 5 170 171 #define TIMER1IPC IPC1 172 #define TIMER2IPC IPC2 173 #define TIMER3IPC IPC3 174 #define TIMER4IPC IPC4 175 #define TIMER5IPC IPC5 176 #define TIMERIPCBASE 0 177 178 /* UART conveniences. */ 179 180 #define U1MODE 0xBF806000 181 #define U2MODE 0xBF806200 182 183 #define UARTMIN 1 184 #define UARTMAX 2 185 #define UARTBASE U1MODE 186 #define UARTSTEP (U2MODE - U1MODE) 187 188 #define UxMODE 0x00 189 #define UxSTA 0x10 190 #define UxTXREG 0x20 191 #define UxRXREG 0x30 192 #define UxBRG 0x40 193 194 #define UARTIEC IEC1 195 196 #define UxEIE 1 197 #define UxRIE 2 198 #define UxTIE 4 199 200 #define UARTIFS IFS1 201 202 #define UxEIF 1 203 #define UxRIF 2 204 #define UxTIF 4 205 206 #define UARTINTBASE 7 207 #define UARTINTSTEP 14 208 209 #define UART1IPC IPC8 210 #define UART1IPCBASE 0 211 #define UART2IPC IPC9 212 #define UART2IPCBASE 8 213 214 /* Interrupt numbers. 215 * See... 216 * TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION 217 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 218 */ 219 220 #define DMA0 60 221 #define DMA1 61 222 #define DMA2 62 223 #define DMA3 63 224 #define OC1 7 225 #define OC2 12 226 #define OC3 17 227 #define OC4 22 228 #define OC5 27 229 #define T1 4 230 #define T2 9 231 #define T3 14 232 #define T4 19 233 #define T5 24 234 #define U1RX 40 235 #define U1TX 41 236 #define U2RX 54 237 #define U2TX 55 238 239 /* Address modifiers. 240 * See... 241 * 11.2 CLR, SET and INV Registers 242 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 243 */ 244 245 #define CLR 0x4 246 #define SET 0x8 247 #define INV 0xC 248 249 #endif /* __PIC32_H__ */