1 /* 2 * PIC32 peripheral descriptions. 3 * 4 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __PIC32_H__ 21 #define __PIC32_H__ 22 23 /* Peripheral addresses. 24 * See... 25 * TABLE 4-1: SFR MEMORYMAP 26 * TABLE 11-3: PORTA REGISTER MAP 27 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 28 */ 29 30 #define OSCCON 0xBF80F000 31 #define REFOCON 0xBF80F020 32 #define REFOTRIM 0xBF80F030 33 #define CFGCON 0xBF80F200 34 #define SYSKEY 0xBF80F230 35 36 #define INT2R 0xBF80FA08 37 #define U1RXR 0xBF80FA50 38 39 #define RPA0R 0xBF80FB00 40 #define RPA1R 0xBF80FB04 41 #define RPA2R 0xBF80FB08 42 #define RPA3R 0xBF80FB0C 43 #define RPA4R 0xBF80FB10 44 #define RPB0R 0xBF80FB2C 45 #define RPB1R 0xBF80FB30 46 #define RPB2R 0xBF80FB34 47 #define RPB3R 0xBF80FB38 48 #define RPB4R 0xBF80FB3C 49 #define RPB5R 0xBF80FB40 50 #define RPB10R 0xBF80FB54 51 #define RPB15R 0xBF80FB68 52 53 #define INTCON 0xBF881000 54 #define IFS0 0xBF881030 55 #define IFS1 0xBF881040 56 #define IEC0 0xBF881060 57 #define IEC1 0xBF881070 58 #define IPC0 0xBF881090 59 #define IPC1 0xBF8810A0 60 #define IPC2 0xBF8810B0 61 #define IPC3 0xBF8810C0 62 #define IPC4 0xBF8810D0 63 #define IPC5 0xBF8810E0 64 #define IPC6 0xBF8810F0 65 #define IPC7 0xBF881100 66 #define IPC8 0xBF881110 67 #define IPC9 0xBF881120 68 #define IPC10 0xBF881130 69 70 #define BMXCON 0xBF882000 71 #define BMXDKPBA 0xBF882010 72 #define BMXDUDBA 0xBF882020 73 #define BMXDUPBA 0xBF882030 74 #define BMXDRMSZ 0xBF882040 75 76 #define ANSELA 0xBF886000 77 #define TRISA 0xBF886010 78 #define PORTA 0xBF886020 79 #define LATA 0xBF886030 80 #define ODCA 0xBF886040 81 #define ANSELB 0xBF886100 82 #define TRISB 0xBF886110 83 #define PORTB 0xBF886120 84 #define LATB 0xBF886130 85 #define ODCB 0xBF886140 86 87 /* DEVCFG conveniences. */ 88 89 #define DEVCFG1_UNUSED 0xff7fcbd8 /* exclude FWDTWINSZ, WINDIS, WDTPS, FCKSM, POSCMOD, IESO */ 90 91 #define DEVCFG1_FWDTEN_OFF (0 << 23) 92 #define DEVCFG1_FWDTEN_ON (1 << 23) 93 94 #define DEVCFG1_FPBDIV_1 (0b00 << 12) 95 #define DEVCFG1_FPBDIV_2 (0b01 << 12) 96 #define DEVCFG1_FPBDIV_4 (0b10 << 12) 97 #define DEVCFG1_FPBDIV_8 (0b11 << 12) 98 99 #define DEVCFG1_OSCIOFNC_ON (0 << 10) 100 #define DEVCFG1_OSCIOFNC_OFF (1 << 10) 101 102 #define DEVCFG1_FSOSCEN_OFF (0 << 5) 103 #define DEVCFG1_FSOSCEN_ON (1 << 5) 104 105 #define DEVCFG1_FNOSC_FRC (0b000) 106 #define DEVCFG1_FNOSC_FRCDIV_PLL (0b001) 107 #define DEVCFG1_FNOSC_FRCDIV (0b111) 108 109 #define DEVCFG2_UNUSED 0xfff8ff88 /* exclude UPLLEN, UPLLIDIV */ 110 111 #define DEVCFG2_FPLLODIV_1 (0b000 << 16) 112 #define DEVCFG2_FPLLODIV_2 (0b001 << 16) 113 #define DEVCFG2_FPLLODIV_4 (0b010 << 16) 114 #define DEVCFG2_FPLLODIV_8 (0b011 << 16) 115 #define DEVCFG2_FPLLODIV_16 (0b100 << 16) 116 #define DEVCFG2_FPLLODIV_32 (0b101 << 16) 117 #define DEVCFG2_FPLLODIV_64 (0b110 << 16) 118 #define DEVCFG2_FPLLODIV_128 (0b111 << 16) 119 120 #define DEVCFG2_FPLLMUL_15 (0b000 << 4) 121 #define DEVCFG2_FPLLMUL_16 (0b001 << 4) 122 #define DEVCFG2_FPLLMUL_17 (0b010 << 4) 123 #define DEVCFG2_FPLLMUL_18 (0b011 << 4) 124 #define DEVCFG2_FPLLMUL_19 (0b100 << 4) 125 #define DEVCFG2_FPLLMUL_20 (0b101 << 4) 126 #define DEVCFG2_FPLLMUL_21 (0b110 << 4) 127 #define DEVCFG2_FPLLMUL_24 (0b111 << 4) 128 129 #define DEVCFG2_FPLLIDIV_1 (0b000) 130 #define DEVCFG2_FPLLIDIV_2 (0b001) 131 #define DEVCFG2_FPLLIDIV_3 (0b010) 132 #define DEVCFG2_FPLLIDIV_4 (0b011) 133 #define DEVCFG2_FPLLIDIV_5 (0b100) 134 #define DEVCFG2_FPLLIDIV_6 (0b101) 135 #define DEVCFG2_FPLLIDIV_10 (0b110) 136 #define DEVCFG2_FPLLIDIV_12 (0b111) 137 138 /* DMA conveniences. */ 139 140 #define DMACON 0xBF883000 141 #define DCH0CON 0xBF883060 142 #define DCH1CON 0xBF883120 143 #define DCH2CON 0xBF8831E0 144 #define DCH3CON 0xBF8832A0 145 146 #define DCHMIN 0 147 #define DCHMAX 3 148 #define DCHBASE DCH0CON 149 #define DCHSTEP (DCH1CON - DCH0CON) 150 151 #define DCHxCON 0x00 152 #define DCHxECON 0x10 153 #define DCHxINT 0x20 154 #define DCHxSSA 0x30 155 #define DCHxDSA 0x40 156 #define DCHxSSIZ 0x50 157 #define DCHxDSIZ 0x60 158 #define DCHxSPTR 0x70 159 #define DCHxDPTR 0x80 160 #define DCHxCSIZ 0x90 161 #define DCHxCPTR 0xA0 162 #define DCHxDAT 0xB0 163 164 #define DMAIEC IEC1 165 166 #define DCHxIE 1 167 168 #define DMAIFS IFS1 169 170 #define DCHxIF 1 171 172 #define DMAINTBASE 28 173 174 #define DMAIPC IPC10 175 #define DCHIPCBASE 0 176 #define DCHIPCSTEP 8 177 178 /* External interrupt conveniences. */ 179 180 #define INTMIN 0 181 #define INTMAX 4 182 183 #define INTIEC IEC0 184 185 #define INTxIE 1 186 187 #define INTIFS IFS0 188 189 #define INTxIF 1 190 191 #define INTINTBASE 3 192 #define INTINTSTEP 5 193 194 #define INT0IPC IPC0 195 #define INT1IPC IPC1 196 #define INT2IPC IPC2 197 #define INT3IPC IPC3 198 #define INT4IPC IPC4 199 #define INTIPCBASE 24 200 201 /* Output compare conveniences. */ 202 203 #define OC1CON 0xBF803000 204 #define OC2CON 0xBF803200 205 #define OC3CON 0xBF803400 206 #define OC4CON 0xBF803600 207 #define OC5CON 0xBF803800 208 209 #define OCMIN 1 210 #define OCMAX 5 211 #define OCBASE OC1CON 212 #define OCSTEP (OC2CON - OC1CON) 213 214 #define OCxCON 0x00 215 #define OCxR 0x10 216 #define OCxRS 0x20 217 218 #define OCIEC IEC0 219 220 #define OCxIE 1 221 222 #define OCIFS IFS0 223 224 #define OCxIF 1 225 226 #define OCINTBASE 7 227 #define OCINTSTEP 5 228 229 #define OC1IPC IPC1 230 #define OC2IPC IPC2 231 #define OC3IPC IPC3 232 #define OC4IPC IPC4 233 #define OC5IPC IPC5 234 #define OCIPCBASE 16 235 236 /* Parallel mode conveniences. */ 237 238 #define PMCON 0xBF807000 239 240 #define PMxCON 0x00 241 #define PMxMODE 0x10 242 #define PMxADDR 0x20 243 #define PMxDOUT 0x30 244 #define PMxDIN 0x40 245 #define PMxAEN 0x50 246 #define PMxSTAT 0x60 247 248 #define PMMIN 0 249 #define PMMAX 0 250 #define PMBASE PMCON 251 #define PMSTEP 0 252 253 #define PMIEC IEC1 254 255 #define PMxIE 1 256 #define PMxEIE 2 257 258 #define PMIFS IFS1 259 260 #define PMxIF 1 261 #define PMxEIF 2 262 263 #define PMINTBASE 16 264 #define PMINTSTEP 0 265 266 #define PMIPC IPC8 267 #define PMIPCBASE 24 268 269 /* Timer conveniences. */ 270 271 #define T1CON 0xBF800600 272 #define T2CON 0xBF800800 273 #define T3CON 0xBF800A00 274 #define T4CON 0xBF800C00 275 #define T5CON 0xBF800E00 276 277 #define TIMERMIN 1 278 #define TIMERMAX 5 279 #define TIMERBASE T1CON 280 #define TIMERSTEP (T2CON - T1CON) 281 282 #define TxCON 0x00 283 #define TMRx 0x10 284 #define PRx 0x20 285 286 #define TIMERIEC IEC0 287 288 #define TxIE 1 289 290 #define TIMERIFS IFS0 291 292 #define TxIF 1 293 294 #define TIMERINTBASE 4 295 #define TIMERINTSTEP 5 296 297 #define TIMER1IPC IPC1 298 #define TIMER2IPC IPC2 299 #define TIMER3IPC IPC3 300 #define TIMER4IPC IPC4 301 #define TIMER5IPC IPC5 302 #define TIMERIPCBASE 0 303 304 #define TIMERINTNUMBASE 4 305 #define TIMERINTNUMSTEP 5 306 307 /* UART conveniences. */ 308 309 #define U1MODE 0xBF806000 310 #define U2MODE 0xBF806200 311 312 #define UARTMIN 1 313 #define UARTMAX 2 314 #define UARTBASE U1MODE 315 #define UARTSTEP (U2MODE - U1MODE) 316 317 #define UxMODE 0x00 318 #define UxSTA 0x10 319 #define UxTXREG 0x20 320 #define UxRXREG 0x30 321 #define UxBRG 0x40 322 323 #define UARTIEC IEC1 324 325 #define UxEIE 1 326 #define UxRIE 2 327 #define UxTIE 4 328 329 #define UARTIFS IFS1 330 331 #define UxEIF 1 332 #define UxRIF 2 333 #define UxTIF 4 334 335 #define UARTINTBASE 7 336 #define UARTINTSTEP 14 337 338 #define UART1IPC IPC8 339 #define UART1IPCBASE 0 340 #define UART2IPC IPC9 341 #define UART2IPCBASE 8 342 343 /* Interrupt numbers. 344 * See... 345 * TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION 346 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 347 */ 348 349 #define DMA0 60 350 #define DMA1 61 351 #define DMA2 62 352 #define DMA3 63 353 #define INT0 3 354 #define INT1 8 355 #define INT2 13 356 #define INT3 18 357 #define INT4 23 358 #define OC1 7 359 #define OC2 12 360 #define OC3 17 361 #define OC4 22 362 #define OC5 27 363 #define PMP 48 364 #define PMPE 49 365 #define T1 4 366 #define T2 9 367 #define T3 14 368 #define T4 19 369 #define T5 24 370 #define U1RX 40 371 #define U1TX 41 372 #define U2RX 54 373 #define U2TX 55 374 375 /* Address modifiers. 376 * See... 377 * 11.2 CLR, SET and INV Registers 378 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 379 */ 380 381 #define CLR 0x4 382 #define SET 0x8 383 #define INV 0xC 384 385 #endif /* __PIC32_H__ */