1 Introduction
2 ------------
3
4 This example demonstrates the generation of an analogue VGA signal from a
5 PIC32 microcontroller using general output pins. Unlike the vga and vga-pmp
6 examples, it employs a regular interrupt condition to schedule single-byte
7 (single-pixel) DMA transfers instead of a single whole-line transfer.
8
9 The principal advantage of this method over the whole-line transfer method is
10 its production of pixels with consistent widths. The principal disadvantage is
11 the significant loss of horizontal resolution due to the latencies involved in
12 propagating interrupt conditions to the DMA controller and thereby initiating
13 each transfer.
14
15 Employing a peripheral clock that has half the frequency of the system clock
16 should ensure the stability of the picture, since the lower frequency may make
17 transfers easier to schedule. The peripheral clock should provide a more
18 forgiving deadline for each transfer, permitting late transfers to complete on
19 time.
20
21 Meanwhile, matching the system and peripheral clock frequencies appears to
22 leave the scheduling of transfers open to uncertainty, with transfers being
23 more readily delayed by other activity in the system, and with instability of
24 the picture being the result.
25
26 In contrast to the vga and vga-pmp examples, a special DMA channel is employed
27 to initiate the pixel transfer process without actually transferring any pixel
28 data itself. The channel arrangement is as follows:
29
30 Transfer Initiator DMA Channel Transfer Activity
31 ------------------ ----------- -----------------
32 Timer2 DMA0 zerodata -> PORTB
33 Timer3 DMA1 linedata -> PORTB
34 DMA1 (completion) DMA2 zerodata -> PORTB
35
36 The real purpose of this channel (DMA0) is to capture the Timer2 interrupt
37 condition and to enable the following channel (DMA1) through channel chaining.
38 Having been enabled, DMA1 is then able to conduct transfers at a tempo
39 dictated by Timer3. Finally, DMA2 acts as the "reset" or "zero" channel to
40 ensure that the pixel level is set to black at the end of each display line.
41
42 In principle, other initiating conditions can be used instead of Timer3, which
43 is configured to produce such conditions as frequently as possible:
44
45 * A persistent interrupt condition can be employed instead. For example,
46 configuring UART2 and setting the UART2 transfer interrupt, employing this
47 interrupt condition for DMA1, produces the same effect.
48
49 * An external interrupt such as INT2 can be configured, and the peripheral
50 clock can be routed through the CLKO pin and back into the microcontroller
51 via an appropriate pin. With INT2 being employed as the interrupt
52 condition for DMA1, the same effect is produced.
53
54 Hardware Details
55 ================
56
57 The pin usage of this solution is documented below.
58
59 PIC32MX270F256B-50I/SP Pin Assignments
60 --------------------------------------
61
62 MCLR# 1 \/ 28
63 HSYNC/OC1/RA0 2 27
64 VSYNC/OC2/RA1 3 26 RB15/U1TX
65 D0/RB0 4 25 RB14
66 D1/RB1 5 24 RB13/U1RX
67 D2/RB2 6 23
68 D3/RB3 7 22 RB11/PGEC2
69 8 21 RB10/PGEC3
70 RA2 9 20
71 RA3 10 19
72 D4/RB4 11 18 RB9
73 12 17 RB8
74 13 16 RB7/D7
75 D5/RB5 14 15
76
77 Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
78 unlike the MX170 variant).
79
80 UART Connections
81 ----------------
82
83 UART1 is exposed by the RB13 and RB15 pins.
84
85 Data Signal Routing
86 -------------------
87
88 For one bit of intensity, two bits per colour channel:
89
90 D7 -> 2200R -> I
91
92 I -> diode -> R
93 I -> diode -> G
94 I -> diode -> B
95
96 D6 (not connected)
97
98 D5 -> 470R -> R
99 D4 -> 1000R -> R
100 D3 -> 470R -> G
101 D2 -> 1000R -> G
102 D1 -> 470R -> B
103 D0 -> 1000R -> B
104
105 HSYNC -> HS
106 VSYNC -> VS
107
108 Output Socket Pinout
109 --------------------
110
111 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
112
113 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
114
115 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
116
117 Output Cable Pinout
118 -------------------
119
120 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
121
122 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
123
124 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
125
126 References
127 ----------
128
129 https://en.wikipedia.org/wiki/VGA_connector
130
131 http://papilio.cc/index.php?n=Papilio.VGAWing
132
133 http://lucidscience.com/pro-vga%20video%20generator-2.aspx
134
135 https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga