1 /* 2 * Generate a VGA signal using a PIC32 microcontroller. 3 * 4 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 21 #include "pic32_c.h" 22 #include "init.h" 23 #include "debug.h" 24 25 /* Specific functionality. */ 26 27 #include "main.h" 28 #include "devconfig.h" 29 #include "vga.h" 30 #include "display.h" 31 32 33 34 /* Display state. */ 35 36 static void (*state_handler)(void); 37 static uint32_t line; 38 39 /* Pointers to pixel lines. */ 40 41 static uint8_t *linedata, *linedatalimit, *screenstart; 42 43 /* Pixel data. */ 44 45 static const uint8_t zerodata[ZERO_LENGTH] = {0}; 46 static uint8_t framebuffer[SCREEN_SIZE]; 47 48 49 50 /* Blink an attached LED with delays implemented using a loop. */ 51 52 static void blink(uint32_t delay, uint32_t port, uint32_t pins) 53 { 54 uint32_t counter; 55 56 /* Clear outputs (LED). */ 57 58 CLR_REG(port, pins); 59 60 while (1) 61 { 62 counter = delay; 63 64 while (counter--) __asm__(""); /* retain loop */ 65 66 /* Invert outputs (LED). */ 67 68 INV_REG(port, pins); 69 } 70 } 71 72 73 74 /* Main program. */ 75 76 void main(void) 77 { 78 line = 0; 79 state_handler = vbp_active; 80 test_linedata(framebuffer); 81 82 /* Initialise the current display line pointer and display limit. */ 83 84 linedatalimit = framebuffer + SCREEN_SIZE; 85 screenstart = framebuffer; 86 87 init_memory(); 88 init_pins(); 89 init_outputs(); 90 91 unlock_config(); 92 config_oc(); 93 config_uart(); 94 lock_config(); 95 96 init_dma(); 97 init_pm(); 98 99 /* Configure parallel master mode. */ 100 101 pm_init(0, 0b10); 102 pm_set_output(0, 1, 0); 103 pm_on(0); 104 105 /* Initiate DMA on the Timer2 interrupt transferring line data to the first 106 byte of PORTB. Do not enable the channel for initiation until the visible 107 region is about to start. */ 108 109 dma_init(0, 3); 110 dma_set_auto_enable(0, 1); 111 dma_set_interrupt(0, T2, 1); 112 dma_set_transfer(0, PHYSICAL((uint32_t) linedata), LINE_LENGTH, 113 HW_PHYSICAL(PM_REG(0, PMxDIN)), 1, 114 TRANSFER_CELL_SIZE); 115 116 /* Enable DMA on the preceding channel's completion, with the timer event 117 initiating the transfer. This "reset" or "zero" transfer is employed to 118 set the pixel level to black in a connected flip-flop. Without the 119 flip-flop it is superfluous. */ 120 121 dma_init(1, 3); 122 dma_set_chaining(1, dma_chain_previous); 123 dma_set_interrupt(1, T2, 1); 124 dma_set_transfer(1, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH, 125 HW_PHYSICAL(PM_REG(0, PMxDIN)), 1, 126 ZERO_LENGTH); 127 dma_set_receive_events(1, 1); 128 129 /* Configure a timer for the horizontal sync. The timer has no prescaling 130 (0). */ 131 132 timer_init(2, 0, HFREQ_LIMIT); 133 timer_on(2); 134 135 /* Horizontal sync. */ 136 137 /* Configure output compare in dual compare (continuous output) mode using 138 Timer2 as time base. The interrupt condition drives the first DMA channel 139 and is handled to drive the display state machine. */ 140 141 oc_init(1, 0b101, 2); 142 oc_set_pulse(1, HSYNC_END); 143 oc_set_pulse_end(1, HSYNC_START); 144 oc_init_interrupt(1, 7, 3); 145 oc_on(1); 146 147 /* Vertical sync. */ 148 149 /* Configure output compare in single compare (output driven low) mode using 150 Timer2 as time base. The unit is enabled later. It is only really used to 151 achieve precisely-timed level transitions in hardware. */ 152 153 oc_init(2, 0b010, 2); 154 oc_set_pulse(2, 0); 155 156 uart_init(1, FPB, 115200); 157 uart_on(1); 158 159 interrupts_on(); 160 161 blink(3 << 24, PORTA, 1 << 2); 162 } 163 164 165 166 /* Exception and interrupt handlers. */ 167 168 void exception_handler(void) 169 { 170 blink(3 << 12, PORTA, 1 << 2); 171 } 172 173 void interrupt_handler(void) 174 { 175 uint32_t ifs; 176 177 /* Check for a OC1 interrupt condition. */ 178 179 ifs = REG(OCIFS) & OC_INT_FLAGS(1, OCxIF); 180 181 if (ifs) 182 { 183 line += 1; 184 state_handler(); 185 CLR_REG(OCIFS, ifs); 186 } 187 } 188 189 190 191 /* Vertical back porch region. */ 192 193 void vbp_active(void) 194 { 195 if (line < VISIBLE_START) 196 return; 197 198 /* Enter the visible region. */ 199 200 state_handler = visible_active; 201 202 /* Set the line address. */ 203 204 linedata = screenstart; 205 dma_set_source(0, PHYSICAL((uint32_t) linedata), LINE_LENGTH); 206 207 /* Enable the channel for the next line. */ 208 209 dma_on(0); 210 } 211 212 /* Visible region. */ 213 214 void visible_active(void) 215 { 216 if (line < VFP_START) 217 { 218 /* Update the line address and handle wraparound. */ 219 220 if (!(line % LINE_MULTIPLIER)) 221 { 222 linedata += LINE_LENGTH; 223 if (linedata >= linedatalimit) 224 linedata -= SCREEN_SIZE; 225 } 226 227 dma_set_source(0, PHYSICAL((uint32_t) linedata), LINE_LENGTH); 228 return; 229 } 230 231 /* End the visible region. */ 232 233 state_handler = vfp_active; 234 235 /* Disable the channel for the next line. */ 236 237 dma_off(0); 238 } 239 240 /* Vertical front porch region. */ 241 242 void vfp_active(void) 243 { 244 if (line < VSYNC_START) 245 return; 246 247 /* Enter the vertical sync region. */ 248 249 state_handler = vsync_active; 250 251 /* Bring vsync low (single compare, output driven low) when the next line 252 starts. */ 253 254 oc_init(2, 0b010, 2); 255 oc_on(2); 256 } 257 258 /* Vertical sync region. */ 259 260 void vsync_active(void) 261 { 262 if (line < VSYNC_END) 263 return; 264 265 /* Start again at the top of the display. */ 266 267 line = 0; 268 state_handler = vbp_active; 269 270 /* Bring vsync high (single compare, output driven high) when the next line 271 starts. */ 272 273 oc_init(2, 0b001, 2); 274 oc_on(2); 275 } 276 277 278 279 /* Peripheral pin configuration. */ 280 281 void config_oc(void) 282 { 283 /* Map OC1 to RPB4. */ 284 285 REG(RPB4R) = 0b0101; /* RPB4R<3:0> = 0101 (OC1) */ 286 287 /* Map OC2 to RPB5. */ 288 289 REG(RPB5R) = 0b0101; /* RPB5R<3:0> = 0101 (OC2) */ 290 } 291 292 void config_uart(void) 293 { 294 /* Map U1RX to RPB13. */ 295 296 REG(U1RXR) = 0b0011; /* U1RXR<3:0> = 0011 (RPB13) */ 297 298 /* Map U1TX to RPB15. */ 299 300 REG(RPB15R) = 0b0001; /* RPB15R<3:0> = 0001 (U1TX) */ 301 302 /* Set RPB13 to input. */ 303 304 SET_REG(TRISB, 1 << 13); 305 }