1 /* 2 * PIC32 peripheral configuration and initialisation. 3 * 4 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "cpu.h" 21 #include "pic32_c.h" 22 #include "init.h" 23 24 25 26 /* Basic memory and pin initialisation. */ 27 28 void init_memory(void) 29 { 30 /* 31 Configure RAM. 32 See: http://microchipdeveloper.com/32bit:mx-arch-exceptions-processor-initialization 33 */ 34 35 uint32_t config = REG(BMXCON); 36 37 /* Set zero wait states for address setup. */ 38 39 config &= ~(1 << 6); /* BMXCON<6> = BMXWSDRM = 0 */ 40 41 /* Set bus arbitration mode. */ 42 43 config &= ~0b111; 44 config |= 0b010; /* BMXCON<2:0> = BMXARB<2:0> = 2 */ 45 46 REG(BMXCON) = config; 47 } 48 49 void init_pins(void) 50 { 51 /* DEVCFG0<2> also needs setting to 0 before the program is run. */ 52 53 CLR_REG(CFGCON, 1 << 3); /* CFGCON<3> = JTAGEN = 0 */ 54 } 55 56 void init_outputs(void) 57 { 58 /* Remove analogue features from pins. */ 59 60 REG(ANSELA) = 0; 61 REG(ANSELB) = 0; 62 63 /* Set pins as outputs. */ 64 65 REG(TRISA) = 0; 66 REG(TRISB) = 0; 67 68 /* Clear outputs. */ 69 70 REG(PORTA) = 0; 71 REG(PORTB) = 0; 72 } 73 74 75 76 /* Peripheral pin configuration. */ 77 78 void lock_config(void) 79 { 80 SET_REG(CFGCON, 1 << 13); /* IOLOCK = 1 */ 81 82 /* Lock the configuration again. */ 83 84 REG(SYSKEY) = 0x33333333; 85 } 86 87 void unlock_config(void) 88 { 89 /* Unlock the configuration register bits. */ 90 91 REG(SYSKEY) = 0; 92 REG(SYSKEY) = 0xAA996655; 93 REG(SYSKEY) = 0x556699AA; 94 95 CLR_REG(CFGCON, 1 << 13); /* IOLOCK = 0 */ 96 } 97 98 99 100 /* Convenience operations. */ 101 102 void interrupts_on(void) 103 { 104 init_interrupts(); 105 enable_interrupts(); 106 handle_error_level(); 107 } 108 109 110 111 /* DMA configuration. */ 112 113 void init_dma(void) 114 { 115 /* Disable DMA interrupts (DMAxIE). */ 116 117 CLR_REG(DMAIEC, 0b1111 << DMAINTBASE); 118 119 /* Clear DMA interrupt flags (DMAxIF). */ 120 121 CLR_REG(DMAIFS, 0b1111 << DMAINTBASE); 122 123 /* Enable DMA. */ 124 125 SET_REG(DMACON, 1 << 15); 126 } 127 128 /* Initialise the given channel. */ 129 130 void dma_init(int channel, uint8_t pri) 131 { 132 if ((channel < DCHMIN) || (channel > DCHMAX)) 133 return; 134 135 /* Initialise a channel. */ 136 137 REG(DMA_REG(channel, DCHxCON)) = pri & 0b11; 138 REG(DMA_REG(channel, DCHxECON)) = 0; 139 REG(DMA_REG(channel, DCHxINT)) = 0; 140 } 141 142 /* Set the channel repeated enable mode, enabling it again when a block transfer 143 completes. The documentation describes this as auto-enable. */ 144 145 void dma_set_auto_enable(int channel, int enable) 146 { 147 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 4); 148 } 149 150 /* Set the channel chaining mode. */ 151 152 void dma_set_chaining(int channel, enum dma_chain chain) 153 { 154 (chain != dma_chain_none ? 155 SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 5); 156 157 (chain == dma_chain_next ? 158 SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 8); 159 } 160 161 /* Configure a channel's initiation interrupt. */ 162 163 void dma_set_interrupt(int channel, uint8_t int_num, int enable) 164 { 165 if ((channel < DCHMIN) || (channel > DCHMAX)) 166 return; 167 168 /* Allow an interrupt to trigger the transfer. */ 169 170 REG(DMA_REG(channel, DCHxECON)) = (int_num << 8) | 171 ((enable ? 1 : 0) << 4); 172 } 173 174 /* Configure only the channel's initiation interrupt status. */ 175 176 void dma_set_interrupt_enable(int channel, int enable) 177 { 178 if ((channel < DCHMIN) || (channel > DCHMAX)) 179 return; 180 181 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxECON), 1 << 4); 182 } 183 184 /* Permit the channel to register events while disabled or suspended. A 185 suspended channel is one that is enabled but where the DMA peripheral 186 has been suspended. */ 187 188 void dma_set_receive_events(int channel, int enable) 189 { 190 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 6); 191 } 192 193 /* Set a channel's source. */ 194 195 void dma_set_source(int channel, 196 uint32_t source_start_address, uint16_t source_size) 197 { 198 if ((channel < DCHMIN) || (channel > DCHMAX)) 199 return; 200 201 REG(DMA_REG(channel, DCHxSSIZ)) = source_size; 202 REG(DMA_REG(channel, DCHxSSA)) = source_start_address; 203 } 204 205 /* Set a channel's transfer parameters. */ 206 207 void dma_set_transfer(int channel, 208 uint32_t source_start_address, uint16_t source_size, 209 uint32_t destination_start_address, uint16_t destination_size, 210 uint16_t cell_size) 211 { 212 if ((channel < DCHMIN) || (channel > DCHMAX)) 213 return; 214 215 dma_set_source(channel, source_start_address, source_size); 216 217 REG(DMA_REG(channel, DCHxDSIZ)) = destination_size; 218 REG(DMA_REG(channel, DCHxDSA)) = destination_start_address; 219 REG(DMA_REG(channel, DCHxCSIZ)) = cell_size; 220 } 221 222 /* Configure interrupts caused by the channel. */ 223 224 void dma_init_interrupt(int channel, uint8_t conditions, 225 uint8_t pri, uint8_t sub) 226 { 227 if ((channel < DCHMIN) || (channel > DCHMAX)) 228 return; 229 230 /* Disable channel interrupt and clear interrupt flag. */ 231 232 CLR_REG(DMAIEC, DMA_INT_FLAGS(channel, 1)); 233 CLR_REG(DMAIFS, DMA_INT_FLAGS(channel, 1)); 234 235 /* Produce an interrupt for the provided conditions. */ 236 237 REG(DMA_REG(channel, DCHxINT)) = conditions << 16; 238 239 /* Set interrupt priorities. */ 240 241 REG(DMAIPC) = (REG(DMAIPC) & 242 ~(DMA_IPC_PRI(channel, 7, 3))) | 243 DMA_IPC_PRI(channel, pri, sub); 244 245 /* Enable interrupt. */ 246 247 SET_REG(DMAIEC, DMA_INT_FLAGS(channel, 1)); 248 } 249 250 /* Enable or disable the channel. */ 251 252 void dma_set_enable(int channel, int enable) 253 { 254 if ((channel < DCHMIN) || (channel > DCHMAX)) 255 return; 256 257 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 7); 258 } 259 260 /* Disable a DMA channel. */ 261 262 void dma_off(int channel) 263 { 264 dma_set_enable(channel, 0); 265 } 266 267 /* Enable a DMA channel. */ 268 269 void dma_on(int channel) 270 { 271 dma_set_enable(channel, 1); 272 } 273 274 275 276 /* External interrupt initialisation. */ 277 278 void int_init_interrupt(int int_num, uint8_t pri, uint8_t sub) 279 { 280 if ((int_num < INTMIN) || (int_num > INTMAX)) 281 return; 282 283 /* Disable interrupt and clear interrupt flag. */ 284 285 CLR_REG(INTIEC, INT_INT_FLAGS(int_num, INTxIE)); 286 CLR_REG(INTIFS, INT_INT_FLAGS(int_num, INTxIF)); 287 288 /* Set interrupt priorities. */ 289 290 REG(INT_IPC_REG(int_num)) = (REG(INT_IPC_REG(int_num)) & 291 ~(INT_IPC_PRI(int_num, 7, 3))) | 292 INT_IPC_PRI(int_num, pri, sub); 293 294 /* Enable interrupt. */ 295 296 SET_REG(INTIEC, INT_INT_FLAGS(int_num, INTxIE)); 297 } 298 299 300 301 /* Output compare configuration. */ 302 303 void oc_init(int unit, uint8_t mode, int timer) 304 { 305 if ((unit < OCMIN) || (unit > OCMAX)) 306 return; 307 308 REG(OC_REG(unit, OCxCON)) = (timer == 3 ? (1 << 3) : 0) | (mode & 0b111); 309 } 310 311 /* Set the start value for the pulse. */ 312 313 void oc_set_pulse(int unit, uint32_t start) 314 { 315 if ((unit < OCMIN) || (unit > OCMAX)) 316 return; 317 318 REG(OC_REG(unit, OCxR)) = start; 319 } 320 321 /* Set the end value for the pulse. */ 322 323 void oc_set_pulse_end(int unit, uint32_t end) 324 { 325 if ((unit < OCMIN) || (unit > OCMAX)) 326 return; 327 328 REG(OC_REG(unit, OCxRS)) = end; 329 } 330 331 /* Configure interrupts caused by the unit. */ 332 333 void oc_init_interrupt(int unit, uint8_t pri, uint8_t sub) 334 { 335 if ((unit < OCMIN) || (unit > OCMAX)) 336 return; 337 338 /* Disable interrupt and clear interrupt flag. */ 339 340 CLR_REG(OCIEC, OC_INT_FLAGS(unit, OCxIE)); 341 CLR_REG(OCIFS, OC_INT_FLAGS(unit, OCxIF)); 342 343 /* Set interrupt priorities. */ 344 345 REG(OC_IPC_REG(unit)) = (REG(OC_IPC_REG(unit)) & 346 ~(OC_IPC_PRI(unit, 7, 3))) | 347 OC_IPC_PRI(unit, pri, sub); 348 349 /* Enable interrupt. */ 350 351 SET_REG(OCIEC, OC_INT_FLAGS(unit, OCxIE)); 352 } 353 354 /* Enable a unit. */ 355 356 void oc_on(int unit) 357 { 358 if ((unit < OCMIN) || (unit > OCMAX)) 359 return; 360 361 SET_REG(OC_REG(unit, OCxCON), 1 << 15); 362 } 363 364 365 366 /* Parallel mode configuration. */ 367 368 void init_pm(void) 369 { 370 int i; 371 372 /* Disable PM interrupts (PMxIE). */ 373 374 CLR_REG(PMIEC, 0b11 << PMINTBASE); 375 376 /* Clear PM interrupt flags (PMxIF). */ 377 378 CLR_REG(PMIFS, 0b11 << PMINTBASE); 379 380 /* Disable PM for configuration. */ 381 382 for (i = PMMIN; i <= PMMAX; i++) 383 REG(PM_REG(i, PMxCON)) = 0; 384 } 385 386 /* Configure the parallel mode. */ 387 388 void pm_init(int port, uint8_t mode) 389 { 390 if ((port < PMMIN) || (port > PMMAX)) 391 return; 392 393 REG(PM_REG(port, PMxMODE)) = (mode & 0b11) << 8; 394 REG(PM_REG(port, PMxAEN)) = 0; 395 REG(PM_REG(port, PMxADDR)) = 0; 396 } 397 398 /* Configure output signals. */ 399 400 void pm_set_output(int port, int write_enable, int read_enable) 401 { 402 if ((port < PMMIN) || (port > PMMAX)) 403 return; 404 405 REG(PM_REG(port, PMxCON)) = (write_enable ? (1 << 9) : 0) | 406 (read_enable ? (1 << 8) : 0) | 407 (1 << 1); /* WRSP: PMENB active high */ 408 } 409 410 /* Configure interrupts caused by parallel mode. */ 411 412 void pm_init_interrupt(int port, uint8_t pri, uint8_t sub) 413 { 414 if ((port < PMMIN) || (port > PMMAX)) 415 return; 416 417 /* Disable interrupt and clear interrupt flag. */ 418 419 CLR_REG(PMIEC, PM_INT_FLAGS(port, PMxIE)); 420 CLR_REG(PMIFS, PM_INT_FLAGS(port, PMxIF)); 421 422 /* Set interrupt priorities. */ 423 424 REG(PM_IPC_REG(port)) = (REG(PM_IPC_REG(port)) & 425 ~(PM_IPC_PRI(port, 7, 3))) | 426 PM_IPC_PRI(port, pri, sub); 427 428 /* Enable interrupt. */ 429 430 SET_REG(PMIEC, PM_INT_FLAGS(port, PMxIE)); 431 } 432 433 /* Enable parallel mode. */ 434 435 void pm_on(int port) 436 { 437 if ((port < PMMIN) || (port > PMMAX)) 438 return; 439 440 SET_REG(PM_REG(port, PMxCON), 1 << 15); 441 } 442 443 /* Disable parallel mode. */ 444 445 void pm_off(int port) 446 { 447 if ((port < PMMIN) || (port > PMMAX)) 448 return; 449 450 CLR_REG(PM_REG(port, PMxCON), 1 << 15); 451 } 452 453 454 455 456 /* Timer configuration. */ 457 458 void timer_init(int timer, uint8_t prescale, uint16_t limit) 459 { 460 /* NOTE: Should convert from the real prescale value. */ 461 462 REG(TIMER_REG(timer, TxCON)) = (prescale & 0b111) << 4; 463 REG(TIMER_REG(timer, TMRx)) = 0; 464 REG(TIMER_REG(timer, PRx)) = limit; 465 } 466 467 /* Configure interrupts caused by the timer. */ 468 469 void timer_init_interrupt(int timer, uint8_t pri, uint8_t sub) 470 { 471 if ((timer < TIMERMIN) || (timer > TIMERMAX)) 472 return; 473 474 /* Disable interrupt and clear interrupt flag. */ 475 476 CLR_REG(TIMERIEC, TIMER_INT_FLAGS(timer, TxIE)); 477 CLR_REG(TIMERIFS, TIMER_INT_FLAGS(timer, TxIF)); 478 479 /* Set interrupt priorities. */ 480 481 REG(TIMER_IPC_REG(timer)) = (REG(TIMER_IPC_REG(timer)) & 482 ~(TIMER_IPC_PRI(timer, 7, 3))) | 483 TIMER_IPC_PRI(timer, pri, sub); 484 485 /* Enable interrupt. */ 486 487 SET_REG(TIMERIEC, TIMER_INT_FLAGS(timer, TxIE)); 488 } 489 490 /* Enable a timer. */ 491 492 void timer_on(int timer) 493 { 494 if ((timer < TIMERMIN) || (timer > TIMERMAX)) 495 return; 496 497 SET_REG(TIMER_REG(timer, TxCON), 1 << 15); 498 } 499 500 501 502 /* UART configuration. */ 503 504 void uart_init(int uart, int fpb, uint32_t baudrate) 505 { 506 /* FPB is configured in the devconfig.h file and set in the start.S file. */ 507 508 if ((uart < UARTMIN) || (uart > UARTMAX)) 509 return; 510 511 /* Disable the UART (ON). */ 512 513 CLR_REG(UART_REG(uart, UxMODE), 1 << 15); 514 515 /* Set the baud rate. For example: 516 517 UxBRG<15:0> = BRG 518 = (FPB / (16 * baudrate)) - 1 519 = (24000000 / (16 * 115200)) - 1 520 = 12 521 */ 522 523 REG(UART_REG(uart, UxBRG)) = (fpb / (16 * baudrate)) - 1; 524 } 525 526 /* Configure interrupts caused by the UART. */ 527 528 void uart_init_interrupt(int uart, uint8_t conditions, 529 uint8_t pri, uint8_t sub) 530 { 531 if ((uart < UARTMIN) || (uart > UARTMAX)) 532 return; 533 534 /* Disable interrupts and clear interrupt flags. */ 535 536 CLR_REG(UARTIEC, UART_INT_FLAGS(uart, UxTIE | UxRIE | UxEIE)); 537 CLR_REG(UARTIFS, UART_INT_FLAGS(uart, UxTIF | UxRIF | UxEIF)); 538 539 /* Set priorities: UxIP = pri; UxIS = sub */ 540 541 REG(UART_IPC_REG(uart)) = (REG(UART_IPC_REG(uart)) & 542 ~UART_IPC_PRI(uart, 7, 3)) | 543 UART_IPC_PRI(uart, pri, sub); 544 545 /* Enable interrupts. */ 546 547 SET_REG(UARTIEC, UART_INT_FLAGS(uart, conditions)); 548 } 549 550 /* Enable a UART. */ 551 552 void uart_on(int uart) 553 { 554 if ((uart < UARTMIN) || (uart > UARTMAX)) 555 return; 556 557 /* Enable receive (URXEN) and transmit (UTXEN). */ 558 559 SET_REG(UART_REG(uart, UxSTA), (1 << 12) | (1 << 10)); 560 561 /* Start UART. */ 562 563 SET_REG(UART_REG(uart, UxMODE), 1 << 15); 564 } 565 566 567 568 /* Utility functions. */ 569 570 /* Return encoded interrupt priorities. */ 571 572 static uint8_t PRI(uint8_t pri, uint8_t sub) 573 { 574 return ((pri & 0b111) << 2) | (sub & 0b11); 575 } 576 577 /* Return the DMA interrupt flags for combining with a register. */ 578 579 int DMA_INT_FLAGS(int channel, uint8_t flags) 580 { 581 return (flags & 0b1) << (DMAINTBASE + (channel - DCHMIN)); 582 } 583 584 /* Return encoded DMA interrupt priorities for combining with a register. */ 585 586 uint32_t DMA_IPC_PRI(int channel, uint8_t pri, uint8_t sub) 587 { 588 return PRI(pri, sub) << (DCHIPCBASE + (channel - DCHMIN) * DCHIPCSTEP); 589 } 590 591 /* Return encoded external interrupt priorities for combining with a register. */ 592 593 uint32_t INT_IPC_PRI(int int_num, uint8_t pri, uint8_t sub) 594 { 595 (void) int_num; 596 return PRI(pri, sub) << INTIPCBASE; 597 } 598 599 /* Return the external interrupt priorities register. */ 600 601 uint32_t INT_IPC_REG(int int_num) 602 { 603 switch (int_num) 604 { 605 case 0: return INT0IPC; 606 case 1: return INT1IPC; 607 case 2: return INT2IPC; 608 case 3: return INT3IPC; 609 case 4: return INT4IPC; 610 default: return 0; /* should not occur */ 611 } 612 } 613 614 /* Return the external interrupt flags for combining with a register. */ 615 616 int INT_INT_FLAGS(int int_num, uint8_t flags) 617 { 618 return (flags & 0b1) << (INTINTBASE + (int_num - INTMIN) * INTINTSTEP); 619 } 620 621 /* Return encoded output compare interrupt priorities for combining with a register. */ 622 623 uint32_t OC_IPC_PRI(int unit, uint8_t pri, uint8_t sub) 624 { 625 (void) unit; 626 return PRI(pri, sub) << OCIPCBASE; 627 } 628 629 /* Return the output compare interrupt priorities register. */ 630 631 uint32_t OC_IPC_REG(int unit) 632 { 633 switch (unit) 634 { 635 case 1: return OC1IPC; 636 case 2: return OC2IPC; 637 case 3: return OC3IPC; 638 case 4: return OC4IPC; 639 case 5: return OC5IPC; 640 default: return 0; /* should not occur */ 641 } 642 } 643 644 /* Return the output compare interrupt flags for combining with a register. */ 645 646 int OC_INT_FLAGS(int unit, uint8_t flags) 647 { 648 return (flags & 0b1) << (OCINTBASE + (unit - OCMIN) * OCINTSTEP); 649 } 650 651 /* Return encoded parallel mode interrupt priorities for combining with a register. */ 652 653 uint32_t PM_IPC_PRI(int port, uint8_t pri, uint8_t sub) 654 { 655 (void) port; 656 return PRI(pri, sub) << PMIPCBASE; 657 } 658 659 /* Return the parallel mode interrupt priorities register. */ 660 661 uint32_t PM_IPC_REG(int port) 662 { 663 (void) port; 664 return PMIPC; 665 } 666 667 /* Return the parallel mode interrupt flags for combining with a register. */ 668 669 int PM_INT_FLAGS(int port, uint8_t flags) 670 { 671 return (flags & 0b11) << (PMINTBASE + (port - PMMIN) * PMINTSTEP); 672 } 673 674 /* Return encoded timer interrupt priorities for combining with a register. */ 675 676 uint32_t TIMER_IPC_PRI(int timer, uint8_t pri, uint8_t sub) 677 { 678 (void) timer; 679 return PRI(pri, sub) << TIMERIPCBASE; 680 } 681 682 /* Return the timer interrupt priorities register. */ 683 684 uint32_t TIMER_IPC_REG(int timer) 685 { 686 switch (timer) 687 { 688 case 1: return TIMER1IPC; 689 case 2: return TIMER2IPC; 690 case 3: return TIMER3IPC; 691 case 4: return TIMER4IPC; 692 case 5: return TIMER5IPC; 693 default: return 0; /* should not occur */ 694 } 695 } 696 697 /* Return the timer interrupt flags for combining with a register. */ 698 699 int TIMER_INT_FLAGS(int timer, uint8_t flags) 700 { 701 return (flags & 0b1) << (TIMERINTBASE + (timer - TIMERMIN) * TIMERINTSTEP); 702 } 703 704 /* Return encoded UART interrupt priorities for combining with a register. */ 705 706 uint32_t UART_IPC_PRI(int uart, uint8_t pri, uint8_t sub) 707 { 708 return PRI(pri, sub) << (uart == 1 ? UART1IPCBASE : UART2IPCBASE); 709 } 710 711 /* Return the UART interrupt priorities register. */ 712 713 uint32_t UART_IPC_REG(int uart) 714 { 715 return uart == 1 ? UART1IPC : UART2IPC; 716 } 717 718 /* Return the UART interrupt flags for combining with a register. */ 719 720 int UART_INT_FLAGS(int uart, uint8_t flags) 721 { 722 return (flags & 0b111) << (UARTINTBASE + (uart - UARTMIN) * UARTINTSTEP); 723 }