1 /* 2 * PIC32 peripheral configuration and initialisation. 3 * 4 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "cpu.h" 21 #include "pic32_c.h" 22 #include "init.h" 23 24 25 26 /* Basic memory and pin initialisation. */ 27 28 void init_memory(void) 29 { 30 /* 31 Configure RAM. 32 See: http://microchipdeveloper.com/32bit:mx-arch-exceptions-processor-initialization 33 */ 34 35 uint32_t config = REG(BMXCON); 36 37 /* Set zero wait states for address setup. */ 38 39 config &= ~(1 << 6); /* BMXCON<6> = BMXWSDRM = 0 */ 40 41 /* Set bus arbitration mode. */ 42 43 config &= ~0b111; 44 config |= 0b010; /* BMXCON<2:0> = BMXARB<2:0> = 2 */ 45 46 REG(BMXCON) = config; 47 } 48 49 void init_pins(void) 50 { 51 /* DEVCFG0<2> also needs setting to 0 before the program is run. */ 52 53 CLR_REG(CFGCON, 1 << 3); /* CFGCON<3> = JTAGEN = 0 */ 54 } 55 56 void init_outputs(void) 57 { 58 /* Remove analogue features from pins. */ 59 60 REG(ANSELA) = 0; 61 REG(ANSELB) = 0; 62 63 /* Set pins as outputs. */ 64 65 REG(TRISA) = 0; 66 REG(TRISB) = 0; 67 68 /* Clear outputs. */ 69 70 REG(PORTA) = 0; 71 REG(PORTB) = 0; 72 } 73 74 75 76 /* Peripheral pin configuration. */ 77 78 void lock_config(void) 79 { 80 SET_REG(CFGCON, 1 << 13); /* IOLOCK = 1 */ 81 82 /* Lock the configuration again. */ 83 84 REG(SYSKEY) = 0x33333333; 85 } 86 87 void unlock_config(void) 88 { 89 /* Unlock the configuration register bits. */ 90 91 REG(SYSKEY) = 0; 92 REG(SYSKEY) = 0xAA996655; 93 REG(SYSKEY) = 0x556699AA; 94 95 CLR_REG(CFGCON, 1 << 13); /* IOLOCK = 0 */ 96 } 97 98 99 100 /* Convenience operations. */ 101 102 void interrupts_on(void) 103 { 104 init_interrupts(); 105 enable_interrupts(); 106 handle_error_level(); 107 } 108 109 110 111 /* DMA configuration. */ 112 113 void init_dma(void) 114 { 115 /* Disable DMA interrupts. */ 116 117 CLR_REG(DMAIEC, 0b1111 << DMAINTBASE); /* DMA3IE...DMA0IE = 0 */ 118 119 /* Clear DMA interrupt flags. */ 120 121 CLR_REG(DMAIFS, 0b1111 << DMAINTBASE); /* DMA3IF...DMA0IF = 0 */ 122 123 /* Enable DMA. */ 124 125 SET_REG(DMACON, 1 << 15); 126 } 127 128 /* Initialise the given channel. */ 129 130 void dma_init(int channel, uint8_t pri) 131 { 132 if ((channel < DCHMIN) || (channel > DCHMAX)) 133 return; 134 135 /* Initialise a channel. */ 136 137 REG(DMA_REG(channel, DCHxCON)) = pri & 0b11; 138 REG(DMA_REG(channel, DCHxECON)) = 0; 139 REG(DMA_REG(channel, DCHxINT)) = 0; 140 } 141 142 /* Set the channel repeated enable mode, enabling it again when a block transfer 143 completes. The documentation describes this as auto-enable. */ 144 145 void dma_set_auto_enable(int channel, int enable) 146 { 147 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 4); 148 } 149 150 /* Set the channel chaining mode. */ 151 152 void dma_set_chaining(int channel, enum dma_chain chain) 153 { 154 (chain != dma_chain_none ? 155 SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 5); 156 157 (chain == dma_chain_next ? 158 SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 8); 159 } 160 161 /* Configure a channel's initiation interrupt. */ 162 163 void dma_set_interrupt(int channel, uint8_t int_num, int enable) 164 { 165 if ((channel < DCHMIN) || (channel > DCHMAX)) 166 return; 167 168 /* Allow an interrupt to trigger the transfer. */ 169 170 REG(DMA_REG(channel, DCHxECON)) = (int_num << 8) | 171 ((enable ? 1 : 0) << 4); 172 } 173 174 /* Configure only the channel's initiation interrupt status. */ 175 176 void dma_set_interrupt_enable(int channel, int enable) 177 { 178 if ((channel < DCHMIN) || (channel > DCHMAX)) 179 return; 180 181 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxECON), 1 << 4); 182 } 183 184 /* Permit the channel to register events while disabled or suspended. A 185 suspended channel is one that is enabled but where the DMA peripheral 186 has been suspended. */ 187 188 void dma_set_receive_events(int channel, int enable) 189 { 190 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 6); 191 } 192 193 /* Set a channel's transfer parameters. */ 194 195 void dma_set_transfer(int channel, 196 uint32_t source_start_address, uint16_t source_size, 197 uint32_t destination_start_address, uint16_t destination_size, 198 uint16_t cell_size) 199 { 200 if ((channel < DCHMIN) || (channel > DCHMAX)) 201 return; 202 203 REG(DMA_REG(channel, DCHxSSIZ)) = source_size; 204 REG(DMA_REG(channel, DCHxSSA)) = source_start_address; 205 REG(DMA_REG(channel, DCHxDSIZ)) = destination_size; 206 REG(DMA_REG(channel, DCHxDSA)) = destination_start_address; 207 REG(DMA_REG(channel, DCHxCSIZ)) = cell_size; 208 } 209 210 /* Configure interrupts caused by the channel. */ 211 212 void dma_init_interrupt(int channel, uint8_t conditions, 213 uint8_t pri, uint8_t sub) 214 { 215 if ((channel < DCHMIN) || (channel > DCHMAX)) 216 return; 217 218 /* Disable channel interrupt and clear interrupt flag. */ 219 220 CLR_REG(DMAIEC, DMA_INT_FLAGS(channel, 1)); 221 CLR_REG(DMAIFS, DMA_INT_FLAGS(channel, 1)); 222 223 /* Produce an interrupt for the provided conditions. */ 224 225 REG(DMA_REG(channel, DCHxINT)) = conditions << 16; 226 227 /* Set interrupt priorities. */ 228 229 REG(DMAIPC) = (REG(DMAIPC) & 230 ~(DMA_IPC_PRI(channel, 7, 3))) | 231 DMA_IPC_PRI(channel, pri, sub); 232 233 /* Enable interrupt. */ 234 235 SET_REG(DMAIEC, DMA_INT_FLAGS(channel, 1)); 236 } 237 238 /* Enable or disable the channel. */ 239 240 void dma_set_enable(int channel, int enable) 241 { 242 if ((channel < DCHMIN) || (channel > DCHMAX)) 243 return; 244 245 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 7); 246 } 247 248 /* Disable a DMA channel. */ 249 250 void dma_off(int channel) 251 { 252 dma_set_enable(channel, 0); 253 } 254 255 /* Enable a DMA channel. */ 256 257 void dma_on(int channel) 258 { 259 dma_set_enable(channel, 1); 260 } 261 262 263 264 /* Output compare configuration. */ 265 266 void oc_init(int unit, uint8_t mode, int timer) 267 { 268 if ((unit < OCMIN) || (unit > OCMAX)) 269 return; 270 271 REG(OC_REG(unit, OCxCON)) = (timer == 3 ? (1 << 3) : 0) | (mode & 0b111); 272 } 273 274 /* Set the start value for the pulse. */ 275 276 void oc_set_pulse(int unit, uint32_t start) 277 { 278 if ((unit < OCMIN) || (unit > OCMAX)) 279 return; 280 281 REG(OC_REG(unit, OCxR)) = start; 282 } 283 284 /* Set the end value for the pulse. */ 285 286 void oc_set_pulse_end(int unit, uint32_t end) 287 { 288 if ((unit < OCMIN) || (unit > OCMAX)) 289 return; 290 291 REG(OC_REG(unit, OCxRS)) = end; 292 } 293 294 /* Configure interrupts caused by the unit. */ 295 296 void oc_init_interrupt(int unit, uint8_t pri, uint8_t sub) 297 { 298 if ((unit < OCMIN) || (unit > OCMAX)) 299 return; 300 301 /* Disable interrupt and clear interrupt flag. */ 302 303 CLR_REG(OCIEC, OC_INT_FLAGS(unit, OCxIE)); 304 CLR_REG(OCIFS, OC_INT_FLAGS(unit, OCxIF)); 305 306 /* Set interrupt priorities. */ 307 308 REG(OC_IPC_REG(unit)) = (REG(OC_IPC_REG(unit)) & 309 ~(OC_IPC_PRI(unit, 7, 3))) | 310 OC_IPC_PRI(unit, pri, sub); 311 312 /* Enable interrupt. */ 313 314 SET_REG(OCIEC, OC_INT_FLAGS(unit, OCxIE)); 315 } 316 317 /* Enable a unit. */ 318 319 void oc_on(int unit) 320 { 321 if ((unit < OCMIN) || (unit > OCMAX)) 322 return; 323 324 SET_REG(OC_REG(unit, OCxCON), 1 << 15); 325 } 326 327 328 329 /* Timer configuration. */ 330 331 void timer_init(int timer, uint8_t prescale, uint16_t limit) 332 { 333 /* NOTE: Should convert from the real prescale value. */ 334 335 REG(TIMER_REG(timer, TxCON)) = (prescale & 0b111) << 4; 336 REG(TIMER_REG(timer, TMRx)) = 0; 337 REG(TIMER_REG(timer, PRx)) = limit; 338 } 339 340 /* Configure interrupts caused by the timer. */ 341 342 void timer_init_interrupt(int timer, uint8_t pri, uint8_t sub) 343 { 344 if ((timer < TIMERMIN) || (timer > TIMERMAX)) 345 return; 346 347 /* Disable interrupt and clear interrupt flag. */ 348 349 CLR_REG(TIMERIEC, TIMER_INT_FLAGS(timer, TxIE)); 350 CLR_REG(TIMERIFS, TIMER_INT_FLAGS(timer, TxIF)); 351 352 /* Set interrupt priorities. */ 353 354 REG(TIMER_IPC_REG(timer)) = (REG(TIMER_IPC_REG(timer)) & 355 ~(TIMER_IPC_PRI(timer, 7, 3))) | 356 TIMER_IPC_PRI(timer, pri, sub); 357 358 /* Enable interrupt. */ 359 360 SET_REG(TIMERIEC, TIMER_INT_FLAGS(timer, TxIE)); 361 } 362 363 /* Enable a timer. */ 364 365 void timer_on(int timer) 366 { 367 if ((timer < TIMERMIN) || (timer > TIMERMAX)) 368 return; 369 370 SET_REG(TIMER_REG(timer, TxCON), 1 << 15); 371 } 372 373 374 375 /* UART configuration. */ 376 377 void uart_init(int uart, uint32_t baudrate) 378 { 379 /* NOTE: Configured in the initial payload. */ 380 381 uint32_t FPB = 24000000; 382 383 if ((uart < UARTMIN) || (uart > UARTMAX)) 384 return; 385 386 /* Disable the UART (ON). */ 387 388 CLR_REG(UART_REG(uart, UxMODE), 1 << 15); 389 390 /* Set the baud rate. For example: 391 392 UxBRG<15:0> = BRG 393 = (FPB / (16 * baudrate)) - 1 394 = (24000000 / (16 * 115200)) - 1 395 = 12 396 */ 397 398 REG(UART_REG(uart, UxBRG)) = (FPB / (16 * baudrate)) - 1; 399 } 400 401 /* Configure interrupts caused by the UART. */ 402 403 void uart_init_interrupt(int uart, uint8_t conditions, 404 uint8_t pri, uint8_t sub) 405 { 406 if ((uart < UARTMIN) || (uart > UARTMAX)) 407 return; 408 409 /* Disable interrupts and clear interrupt flags. */ 410 411 CLR_REG(UARTIEC, UART_INT_FLAGS(uart, UxTIE | UxRIE | UxEIE)); 412 CLR_REG(UARTIFS, UART_INT_FLAGS(uart, UxTIF | UxRIF | UxEIF)); 413 414 /* Set priorities: UxIP = pri; UxIS = sub */ 415 416 REG(UART_IPC_REG(uart)) = (REG(UART_IPC_REG(uart)) & 417 ~UART_IPC_PRI(uart, 7, 3)) | 418 UART_IPC_PRI(uart, pri, sub); 419 420 /* Enable interrupts. */ 421 422 SET_REG(UARTIEC, UART_INT_FLAGS(uart, conditions)); 423 } 424 425 /* Enable a UART. */ 426 427 void uart_on(int uart) 428 { 429 if ((uart < UARTMIN) || (uart > UARTMAX)) 430 return; 431 432 /* Enable receive (URXEN) and transmit (UTXEN). */ 433 434 SET_REG(UART_REG(uart, UxSTA), (1 << 12) | (1 << 10)); 435 436 /* Start UART. */ 437 438 SET_REG(UART_REG(uart, UxMODE), 1 << 15); 439 } 440 441 442 443 /* Utility functions. */ 444 445 /* Return encoded interrupt priorities. */ 446 447 static uint8_t PRI(uint8_t pri, uint8_t sub) 448 { 449 return ((pri & 0b111) << 2) | (sub & 0b11); 450 } 451 452 /* Return the DMA interrupt flags for combining with a register. */ 453 454 int DMA_INT_FLAGS(int channel, uint8_t flags) 455 { 456 return (flags & 0b1) << (DMAINTBASE + (channel - DCHMIN)); 457 } 458 459 /* Return encoded DMA interrupt priorities for combining with a register. */ 460 461 uint32_t DMA_IPC_PRI(int channel, uint8_t pri, uint8_t sub) 462 { 463 return PRI(pri, sub) << (DCHIPCBASE + (channel - DCHMIN) * DCHIPCSTEP); 464 } 465 466 /* Return encoded output compare interrupt priorities for combining with a register. */ 467 468 uint32_t OC_IPC_PRI(int unit, uint8_t pri, uint8_t sub) 469 { 470 (void) unit; 471 return PRI(pri, sub) << OCIPCBASE; 472 } 473 474 /* Return the output compare interrupt priorities register. */ 475 476 uint32_t OC_IPC_REG(int unit) 477 { 478 switch (unit) 479 { 480 case 1: return OC1IPC; 481 case 2: return OC2IPC; 482 case 3: return OC3IPC; 483 case 4: return OC4IPC; 484 case 5: return OC5IPC; 485 default: return 0; /* should not occur */ 486 } 487 } 488 489 /* Return the output compare interrupt flags for combining with a register. */ 490 491 int OC_INT_FLAGS(int unit, uint8_t flags) 492 { 493 return (flags & 0b1) << (OCINTBASE + (unit - OCMIN) * OCINTSTEP); 494 } 495 496 /* Return encoded timer interrupt priorities for combining with a register. */ 497 498 uint32_t TIMER_IPC_PRI(int timer, uint8_t pri, uint8_t sub) 499 { 500 (void) timer; 501 return PRI(pri, sub) << TIMERIPCBASE; 502 } 503 504 /* Return the timer interrupt priorities register. */ 505 506 uint32_t TIMER_IPC_REG(int timer) 507 { 508 switch (timer) 509 { 510 case 1: return TIMER1IPC; 511 case 2: return TIMER2IPC; 512 case 3: return TIMER3IPC; 513 case 4: return TIMER4IPC; 514 case 5: return TIMER5IPC; 515 default: return 0; /* should not occur */ 516 } 517 } 518 519 /* Return the timer interrupt flags for combining with a register. */ 520 521 int TIMER_INT_FLAGS(int timer, uint8_t flags) 522 { 523 return (flags & 0b1) << (TIMERINTBASE + (timer - TIMERMIN) * TIMERINTSTEP); 524 } 525 526 /* Return encoded UART interrupt priorities for combining with a register. */ 527 528 uint32_t UART_IPC_PRI(int uart, uint8_t pri, uint8_t sub) 529 { 530 return PRI(pri, sub) << (uart == 1 ? UART1IPCBASE : UART2IPCBASE); 531 } 532 533 /* Return the UART interrupt priorities register. */ 534 535 uint32_t UART_IPC_REG(int uart) 536 { 537 return uart == 1 ? UART1IPC : UART2IPC; 538 } 539 540 /* Return the UART interrupt flags for combining with a register. */ 541 542 int UART_INT_FLAGS(int uart, uint8_t flags) 543 { 544 return (flags & 0b111) << (UARTINTBASE + (uart - UARTMIN) * UARTINTSTEP); 545 }