1 = VGA Output Example (Dual-Channel DMA Transfers) = 2 3 This example demonstrates the generation of an analogue [[VGA Signal Output| 4 VGA]] signal from a PIC32 microcontroller using general output pins. It 5 follows on from the work done in the VGAPIC32 project. The result is not 6 entirely satisfactory: 7 8 * Every fourth pixel is wider than the others, this apparently being an 9 artefact of the DMA transfer mechanism. 10 11 It might be possible to introduce some kind of delay and even out the pixel 12 widths, but this has not been investigated with hardware. However, unlike the 13 [[../vga-pmp|vga-pmp]] example, there is no accompanying signal to potentially 14 orchestrate the staging of individual pixels at a slightly delayed rate. 15 Potentially, the peripheral clock signal might be generated and processed to 16 make such a signal. 17 18 Unlike the [[../vga|vga]] example, this example employs two DMA channels for 19 pixel data which are interleaved to investigate a potential remedy for the 20 wide pixel effect. Unfortunately, despite each channel contributing every 21 other word (or group of four pixels), the effect persists. However, the 22 picture is perhaps more stable than in the [[../vga|vga]] example. 23 24 One significant problem with this example is that scrolling causes the DMA 25 channels to become ordered incorrectly. This does not affect the 26 [[../vga-timer|vga-timer]] example which also employs two DMA channels. 27 28 == Hardware Details == 29 30 The pin usage of this solution is documented below. 31 32 === PIC32MX270F256B-50I/SP Pin Assignments === 33 34 {{{ 35 MCLR# 1 \/ 28 36 HSYNC/OC1/RA0 2 27 37 VSYNC/OC2/RA1 3 26 RB15/U1TX 38 D0/RB0 4 25 RB14 39 D1/RB1 5 24 RB13/U1RX 40 D2/RB2 6 23 41 D3/RB3 7 22 RB11/PGEC2 42 8 21 RB10/PGED2 43 RA2 9 20 44 RA3 10 19 45 D4/RB4 11 18 RB9 46 12 17 RB8 47 13 16 RB7/D7 48 D5/RB5 14 15 49 }}} 50 51 Note that RB6 is not available on pin 15 on this device (it is needed for VBUS 52 unlike the MX170 variant). 53 54 === UART Connections === 55 56 UART1 is exposed by the RB13 and RB15 pins. 57 58 === Data Signal Routing === 59 60 For one bit of intensity, two bits per colour channel: 61 62 {{{ 63 D7 -> 2200R -> I 64 65 I -> diode -> R 66 I -> diode -> G 67 I -> diode -> B 68 69 D6 (not connected) 70 71 D5 -> 470R -> R 72 D4 -> 1000R -> R 73 D3 -> 470R -> G 74 D2 -> 1000R -> G 75 D1 -> 470R -> B 76 D0 -> 1000R -> B 77 78 HSYNC -> HS 79 VSYNC -> VS 80 }}}