1 /* 2 * PIC32 peripheral descriptions. 3 * 4 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __PIC32_H__ 21 #define __PIC32_H__ 22 23 /* Peripheral addresses. 24 * See... 25 * TABLE 4-1: SFR MEMORYMAP 26 * TABLE 11-3: PORTA REGISTER MAP 27 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 28 */ 29 30 #define PMCON 0xBF807000 31 #define PMMODE 0xBF807010 32 #define PMADDR 0xBF807020 33 #define PMDOUT 0xBF807030 34 #define PMDIN 0xBF807040 35 #define PMAEN 0xBF807050 36 #define PMSTAT 0xBF807060 37 38 #define OSCCON 0xBF80F000 39 #define REFOCON 0xBF80F020 40 #define REFOTRIM 0xBF80F030 41 #define CFGCON 0xBF80F200 42 #define SYSKEY 0xBF80F230 43 44 #define INT2R 0xBF80FA08 45 #define U1RXR 0xBF80FA50 46 47 #define RPA0R 0xBF80FB00 48 #define RPA1R 0xBF80FB04 49 #define RPA2R 0xBF80FB08 50 #define RPA3R 0xBF80FB0C 51 #define RPA4R 0xBF80FB10 52 #define RPB0R 0xBF80FB2C 53 #define RPB1R 0xBF80FB30 54 #define RPB2R 0xBF80FB34 55 #define RPB3R 0xBF80FB38 56 #define RPB4R 0xBF80FB3C 57 #define RPB5R 0xBF80FB40 58 #define RPB10R 0xBF80FB54 59 #define RPB15R 0xBF80FB68 60 61 #define INTCON 0xBF881000 62 #define IFS0 0xBF881030 63 #define IFS1 0xBF881040 64 #define IEC0 0xBF881060 65 #define IEC1 0xBF881070 66 #define IPC0 0xBF881090 67 #define IPC1 0xBF8810A0 68 #define IPC2 0xBF8810B0 69 #define IPC3 0xBF8810C0 70 #define IPC4 0xBF8810D0 71 #define IPC5 0xBF8810E0 72 #define IPC6 0xBF8810F0 73 #define IPC7 0xBF881100 74 #define IPC8 0xBF881110 75 #define IPC9 0xBF881120 76 #define IPC10 0xBF881130 77 78 #define BMXCON 0xBF882000 79 #define BMXDKPBA 0xBF882010 80 #define BMXDUDBA 0xBF882020 81 #define BMXDUPBA 0xBF882030 82 #define BMXDRMSZ 0xBF882040 83 84 #define ANSELA 0xBF886000 85 #define TRISA 0xBF886010 86 #define PORTA 0xBF886020 87 #define LATA 0xBF886030 88 #define ODCA 0xBF886040 89 #define ANSELB 0xBF886100 90 #define TRISB 0xBF886110 91 #define PORTB 0xBF886120 92 #define LATB 0xBF886130 93 #define ODCB 0xBF886140 94 95 /* DMA conveniences. */ 96 97 #define DMACON 0xBF883000 98 #define DCH0CON 0xBF883060 99 #define DCH1CON 0xBF883120 100 #define DCH2CON 0xBF8831E0 101 #define DCH3CON 0xBF8832A0 102 103 #define DCHMIN 0 104 #define DCHMAX 3 105 #define DCHBASE DCH0CON 106 #define DCHSTEP (DCH1CON - DCH0CON) 107 108 #define DCHxCON 0x00 109 #define DCHxECON 0x10 110 #define DCHxINT 0x20 111 #define DCHxSSA 0x30 112 #define DCHxDSA 0x40 113 #define DCHxSSIZ 0x50 114 #define DCHxDSIZ 0x60 115 #define DCHxSPTR 0x70 116 #define DCHxDPTR 0x80 117 #define DCHxCSIZ 0x90 118 #define DCHxCPTR 0xA0 119 #define DCHxDAT 0xB0 120 121 #define DMAIEC IEC1 122 123 #define DCHxIE 1 124 125 #define DMAIFS IFS1 126 127 #define DCHxIF 1 128 129 #define DMAINTBASE 28 130 131 #define DMAIPC IPC10 132 #define DCHIPCBASE 0 133 #define DCHIPCSTEP 8 134 135 /* External interrupt conveniences. */ 136 137 #define INTMIN 0 138 #define INTMAX 4 139 140 #define INTIEC IEC0 141 142 #define INTxIE 1 143 144 #define INTIFS IFS0 145 146 #define INTxIF 1 147 148 #define INTINTBASE 3 149 #define INTINTSTEP 5 150 151 #define INT0IPC IPC0 152 #define INT1IPC IPC1 153 #define INT2IPC IPC2 154 #define INT3IPC IPC3 155 #define INT4IPC IPC4 156 #define INTIPCBASE 24 157 158 /* Output compare conveniences. */ 159 160 #define OC1CON 0xBF803000 161 #define OC2CON 0xBF803200 162 #define OC3CON 0xBF803400 163 #define OC4CON 0xBF803600 164 #define OC5CON 0xBF803800 165 166 #define OCMIN 1 167 #define OCMAX 5 168 #define OCBASE OC1CON 169 #define OCSTEP (OC2CON - OC1CON) 170 171 #define OCxCON 0x00 172 #define OCxR 0x10 173 #define OCxRS 0x20 174 175 #define OCIEC IEC0 176 177 #define OCxIE 1 178 179 #define OCIFS IFS0 180 181 #define OCxIF 1 182 183 #define OCINTBASE 7 184 #define OCINTSTEP 5 185 186 #define OC1IPC IPC1 187 #define OC2IPC IPC2 188 #define OC3IPC IPC3 189 #define OC4IPC IPC4 190 #define OC5IPC IPC5 191 #define OCIPCBASE 16 192 193 /* Timer conveniences. */ 194 195 #define T1CON 0xBF800600 196 #define T2CON 0xBF800800 197 #define T3CON 0xBF800A00 198 #define T4CON 0xBF800C00 199 #define T5CON 0xBF800E00 200 201 #define TIMERMIN 1 202 #define TIMERMAX 5 203 #define TIMERBASE T1CON 204 #define TIMERSTEP (T2CON - T1CON) 205 206 #define TxCON 0x00 207 #define TMRx 0x10 208 #define PRx 0x20 209 210 #define TIMERIEC IEC0 211 212 #define TxIE 1 213 214 #define TIMERIFS IEC0 215 216 #define TxIF 1 217 218 #define TIMERINTBASE 4 219 #define TIMERINTSTEP 5 220 221 #define TIMER1IPC IPC1 222 #define TIMER2IPC IPC2 223 #define TIMER3IPC IPC3 224 #define TIMER4IPC IPC4 225 #define TIMER5IPC IPC5 226 #define TIMERIPCBASE 0 227 228 /* UART conveniences. */ 229 230 #define U1MODE 0xBF806000 231 #define U2MODE 0xBF806200 232 233 #define UARTMIN 1 234 #define UARTMAX 2 235 #define UARTBASE U1MODE 236 #define UARTSTEP (U2MODE - U1MODE) 237 238 #define UxMODE 0x00 239 #define UxSTA 0x10 240 #define UxTXREG 0x20 241 #define UxRXREG 0x30 242 #define UxBRG 0x40 243 244 #define UARTIEC IEC1 245 246 #define UxEIE 1 247 #define UxRIE 2 248 #define UxTIE 4 249 250 #define UARTIFS IFS1 251 252 #define UxEIF 1 253 #define UxRIF 2 254 #define UxTIF 4 255 256 #define UARTINTBASE 7 257 #define UARTINTSTEP 14 258 259 #define UART1IPC IPC8 260 #define UART1IPCBASE 0 261 #define UART2IPC IPC9 262 #define UART2IPCBASE 8 263 264 /* Interrupt numbers. 265 * See... 266 * TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION 267 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 268 */ 269 270 #define DMA0 60 271 #define DMA1 61 272 #define DMA2 62 273 #define DMA3 63 274 #define INT0 3 275 #define INT1 8 276 #define INT2 13 277 #define INT3 18 278 #define INT4 23 279 #define OC1 7 280 #define OC2 12 281 #define OC3 17 282 #define OC4 22 283 #define OC5 27 284 #define T1 4 285 #define T2 9 286 #define T3 14 287 #define T4 19 288 #define T5 24 289 #define U1RX 40 290 #define U1TX 41 291 #define U2RX 54 292 #define U2TX 55 293 294 /* Address modifiers. 295 * See... 296 * 11.2 CLR, SET and INV Registers 297 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 298 */ 299 300 #define CLR 0x4 301 #define SET 0x8 302 #define INV 0xC 303 304 #endif /* __PIC32_H__ */